Trong Huynh Bao
Orcid: 0000-0001-9095-8631
According to our database1,
Trong Huynh Bao
authored at least 7 papers
between 2013 and 2019.
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Bibliography
2019
Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2017
Statistical Timing Analysis Considering Device and Interconnect Variability for BEOL Requirements in the 5-nm Node and Beyond.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Cross-layer design and analysis of a low power, high density STT-MRAM for embedded systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017
2015
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
2014
Circuit and process co-design with vertical gate-all-around nanowire FET technology to extend CMOS scaling for 5nm and beyond technologies.
Proceedings of the 44th European Solid State Device Research Conference, 2014
2013
Proceedings of the 8th International Design and Test Symposium, 2013