Trevor W. Fox

EURASIP J. Adv. Signal Process., 2004

2003

Rapid Prototyping of Field Programmable Gate Array-Based Discrete Cosine Transform Approximations.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2003

A Methodology for Rapid Prototyping Peak-Constrained Least-Squares Bit-Serial Finite Impulse Response Filters in FPGAs.

[BibT_eX]

[DOI]

EURASIP J. Adv. Signal Process., 2003

The Design of Low-Power Fixed-Point FIR Differentiator IP Blocks.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

The Multiplier Tree FIR filter architecture.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003

2002

Low coefficient complexity approximations of the one dimensional discrete cosine transform.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A method of implementing bit-serial LDI ladder filters in FPGAs using JBits.

[BibT_eX]

[DOI]

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Implementing the Discrete Cosine Transform Using the Xilinx Virtex FPGA.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

A Method for Implementing Bit-Serial Finite Impulse Response Digital Filters in FPGAs Using JBits<sup>TM</sup>.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

The design of peak constrained least squares FIR filters with low complexity finite precision coefficients.

[BibT_eX]

[DOI]