Travis N. Blalock

According to our database1, Travis N. Blalock authored at least 15 papers between 2001 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A -102dBm Sensitivity, 2.2μA Packet-Level-Duty-cycled Wake-Up Receiver with ADPLL achieving -30dB SIR.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2012
Tracking On-Chip Age Using Distributed, Embedded Sensors.
IEEE Trans. Very Large Scale Integr. Syst., 2012

2010
An Energy-Efficient Subthreshold Level Converter in 130-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2010

SRAM-based NBTI/PBTI sensor system design.
Proceedings of the 47th Design Automation Conference, 2010

2009
Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

A 2.6 µW sub-threshold mixed-signal ECG SoC.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Sub-threshold Operation and Cross-hierarchy Design for Ultra Low Power Wearable Sensors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Mobile health monitoring through biotelemetry.
Proceedings of the 4th International ICST Conference on Body Area Networks, 2009

2008
Experimental System Prototype of a Portable, Low-Cost, C-Scan Ultrasound Imaging Device.
IEEE Trans. Biomed. Eng., 2008

2007
An automated unique tagging system using CMOS process variation.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2005
A three-level toggle-avoid bus signaling scheme.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
An On-Chip Signal Suppression Countermeasure to Power Analysis Attacks.
IEEE Trans. Dependable Secur. Comput., 2004

2003
A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

40 MHz 0.25 um CMOS embedded 1T bit-line decoupled DRAM FIFO for mixed-signal applications.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003

2001
True color 1024×768 microdisplay with analog in-pixel pulsewidth modulation and retinal averaging offset correction.
IEEE J. Solid State Circuits, 2001


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