Travis Hebig

According to our database, Travis Hebig authored at least 3 papers between 2012 and 2013.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2013

A 32 nm 0.58-fJ/Bit/Search 1-GHz Ternary Content Addressable Memory Compiler Using Silicon-Aware Early-Predict Late-Correct Sensing With Embedded Deep-Trench Capacitor Noise Mitigation.

Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort

IEEE J. Solid State Circuits, 2013

Tail-Bit Tracking circuit with degraded VGS bit-cell mimic array for a 50% search-time and 200mV Vmin improvement in a Ternary Content Addressable Memory.

Igor Arsovski, Travis Hebig, John Goss, Paul Grzymkowski, Josh Patch

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012

1Gsearch/sec Ternary Content Addressable Memory compiler with silicon-aware Early-Predict Late-Correct single-ended sensing.

Igor Arsovski, Travis Hebig, Daniel Dobson, Reid Wistort

Proceedings of the Symposium on VLSI Circuits, 2012