Trailokya Nath Sasamal

According to our database, Trailokya Nath Sasamal authored at least 11 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Placement and routing approach for MQCA-based designs with BFS and A* algorithms.

Vineet Jaiswal, Trailokya Nath Sasamal

Comput. Electr. Eng., 2024

2023

A Novel Approach to Design Multiplexer Using Magnetic Quantum-Dot Cellular Automata.

Vineet Jaiswal, Trailokya Nath Sasamal

IEEE Embed. Syst. Lett., September, 2023

Novel approach for the design of efficient full adder in MQCA.

Vineet Jaiswal, Trailokya Nath Sasamal

J. Supercomput., May, 2023

2022

Guest editorial: Introduction to the special section on recent advances and challenges in quantum-dot cellular automata (VSI-QCA).

Ashutosh Kumar Singh, Trailokya Nath Sasamal, Lau Siong Hoe, P. W. Chandana Prasad, Saeed Rasouli Heikalabad

Comput. Electr. Eng., 2022

High Speed Comparator and Parity generator in QCA based on optimal XOR structure.

Trailokya Nath Sasamal, Gaurav Saini, Vineet Jaiswal

Proceedings of the 7th IEEE Forum on Research and Technologies for Society and Industry Innovation, 2022

2020

Quantum-Dot Cellular Automata Based Digital Logic Circuits: A Design Perspective

Trailokya Nath Sasamal, Ashutosh Kumar Singh, Anand Mohan

Studies in Computational Intelligence 879, Springer, ISBN: 978-981-15-1822-5, 2020

2019

Design and Implementation of QCA D-Flip-Flops and RAM Cell Using Majority Gates.

Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar

J. Circuits Syst. Comput., 2019

2018

Efficient Design of Reversible Logic ALU Using Coplanar Quantum-Dot Cellular Automata.

Trailokya Nath Sasamal, Anand Mohan, Ashutosh Kumar Singh

J. Circuits Syst. Comput., 2018

Efficient design of coplanar ripple carry adder in QCA.

Trailokya Nath Sasamal, Ashutosh Kumar Singh, Umesh Ghanekar

IET Circuits Devices Syst., 2018

An efficient design of Vedic multiplier using ripple carry adder in Quantum-dot Cellular Automata.

Ashvin Chudasama, Trailokya Nath Sasamal, Jyoti Yadav

Comput. Electr. Eng., 2018

2017

Efficient design of full adder and subtractor using 5-input majority gate in QCA.

Ramanand Jaiswal, Trailokya Nath Sasamal

Proceedings of the Tenth International Conference on Contemporary Computing, 2017