Tosiron Adegbija

Kevin Antony Gomez

IEEE Trans. Parallel Distributed Syst., September, 2024

Sparsity-Aware Hardware-Software Co-Design of Spiking Neural Networks: An Overview.

[BibT_eX]

[DOI]

CoRR, 2024

System-Level Design Space Exploration for High-Level Synthesis under End-to-End Latency Constraints.

[BibT_eX]

[DOI]

CoRR, 2024

Are LLMs Any Good for High-Level Synthesis?

[BibT_eX]

[DOI]

CoRR, 2024

Deep Inverse Design for High-Level Synthesis.

[BibT_eX]

[DOI]

CoRR, 2024

Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey.

[BibT_eX]

[DOI]

Alaba Yusuf

IEEE Access, 2024

Message from the Technical Program Chairs; ISVLSI 2024.

[BibT_eX]

[DOI]

Garrett S. Rose

Selçuk Köse

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

PULSE: Parametric Hardware Units for Low-power Sparsity-Aware Convolution Engine.

[BibT_eX]

[DOI]

Ilkin Aliyev

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Skip the Benchmark: Generating System-Level High-Level Synthesis Data using Generative Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

Fine-Tuning Surrogate Gradient Learning for Optimal Hardware Performance in Spiking Neural Networks.

[BibT_eX]

[DOI]

Ilkin Aliyev

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

CHIME: Energy-Efficient STT-RAM-Based Concurrent Hierarchical In-Memory Processing.

[BibT_eX]

[DOI]

Kevin Antony Gomez

Proceedings of the 35th IEEE International Conference on Application-specific Systems, 2024

2023

Design Space Exploration of Sparsity-Aware Application-Specific Spiking Neural Network Accelerators.

[BibT_eX]

[DOI]

Ilkin Aliyev

Kama Svoboda

IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023

Jazznet: A Dataset of Fundamental Piano Patterns for Music Audio Machine Learning Research.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Acoustics, 2023

Efficient System-Level Design Space Exploration for High-Level Synthesis Using Pareto-Optimal Subspace Pruning.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022

Exploring Domain-Specific Architectures for Energy-Efficient Wearable Computing.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2022

A high-level synthesis approach for precisely-timed, energy-efficient embedded systems.

[BibT_eX]

[DOI]

Sustain. Comput. Informatics Syst., 2022

Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads.

[BibT_eX]

[DOI]

Future Gener. Comput. Syst., 2022

A Study of STTRAM-based Page Walker Caches for Energy-Efficient Address Translation.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy.

[BibT_eX]

[DOI]

Kevin Antony Gomez

Proceedings of the IEEE 40th International Conference on Computer Design, 2022

2021

Energy characterization of graph workloads.

[BibT_eX]

[DOI]

Antonino Tumeo

Sustain. Comput. Informatics Syst., 2021

DOSAGE: Generating Domain-Specific Accelerators for Resource-Constrained Computing.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2021

2020

A Survey of Phase Classification Techniques for Characterizing Variable Application Behavior.

[BibT_eX]

[DOI]

Keeley Criswell

IEEE Trans. Parallel Distributed Syst., 2020

Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

ECG-Based Authentication Using Timing-Aware Domain-Specific Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

CONDENSE: A Moving Target Defense Approach for Mitigating Cache Side-Channel Attacks.

[BibT_eX]

[DOI]

Chenxi Dai

IEEE Consumer Electron. Mag., 2020

Message from the Technical Program Chairs iSES 2020.

[BibT_eX]

[DOI]

Yasuhiro Takahashi

Linga Reddy Cenkeramaddi

Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2020

A Study of Runtime Adaptive Prefetching for STTRAM L1 Caches.

[BibT_eX]

[DOI]

Proceedings of the 38th IEEE International Conference on Computer Design, 2020

2019

HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Memory Systems, 2019

Energy and Performance Analysis of STTRAM Caches for Mobile Applications.

[BibT_eX]

[DOI]

Mohamad Hammam Alsafrjalani

Proceedings of the 13th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2019

Evaluating Design Space Subsetting for Multi-Objective Optimization in Configurable Systems.

[BibT_eX]

[DOI]

Lokesh Ramamoorthi

Proceedings of the 20th International Symposium on Quality Electronic Design, 2019

Bit-Wise and Multi-GPU Implementations of the DNA Recombination Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE International Conference on High Performance Computing, 2019

SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the Tenth International Green and Sustainable Computing Conference, 2019

MirrorCache: An Energy-Efficient Relaxed Retention L1 STTRAM Cache.

[BibT_eX]

[DOI]

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

Right-Provisioned IoT Edge Computing: An Overview.

[BibT_eX]

[DOI]

Vinu Vijay Kumar

Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019

2018

PhLock: A Cache Energy Saving Technique Using Phase-Based Cache Locking.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Microprocessor Optimizations for the Internet of Things: A Survey.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

HERMIT: A Benchmark Suite for the Internet of Medical Things.

[BibT_eX]

[DOI]

IEEE Internet Things J., 2018

<i>TaPT</i>: Temperature-Aware Dynamic Cache Optimization for Embedded Systems.

[BibT_eX]

[DOI]

Comput., 2018

Realizing Closed-Loop, Online Tuning and Control for Configurable-Cache Embedded Systems: Progress and Challenges.

[BibT_eX]

[DOI]

Islam Badreldin

Mohamad Hammam Alsafrjalani

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Workload Characterization of the SPEC CPU2017 Benchmark Suite.

[BibT_eX]

[DOI]

Mohamad Hammam Alsafrjalani

Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2018

TaSaT: Thermal-Aware Scheduling and Tuning Algorithm for Heterogeneous and Configurable Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018

LARS: Logically adaptable retention time STT-RAM cache for embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

AMELIA: An application of the Internet of Things for aviation safety.

[BibT_eX]

[DOI]

Jeremiah Pate

Proceedings of the 15th IEEE Annual Consumer Communications & Networking Conference, 2018

2017

A Workload Characterization for the Internet of Medical Things (IoMT).

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

PACT: Priority-Aware Phase-Based Cache Tuning for Embedded Systems.

[BibT_eX]

[DOI]

Sam Gianelli

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Exploiting Configurability as a Defense against Cache Side Channel Attacks.

[BibT_eX]

[DOI]

Chenxi Dai

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Coding for Efficient Caching in Multicore Embedded Systems.

[BibT_eX]

[DOI]

Ravi Tandon

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Application-Specific Autonomic Cache Tuning for General Purpose GPUs.

[BibT_eX]

[DOI]

Proceedings of the 2017 International Conference on Cloud and Autonomic Computing, 2017

2016

Microprocessor Optimizations for the Internet of Things.

[BibT_eX]

[DOI]

CoRR, 2016

Temperature-aware Dynamic Optimization of Embedded Systems.

[BibT_eX]

[DOI]

CoRR, 2016

Phase-Based Dynamic Instruction Window Optimization for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Exploring Configurable Non-Volatile Memory-based Caches for Energy-Efficient Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016

2015

Phase-based Cache Locking for Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

2014

Phase distance mapping: a phase-based cache tuning methodology for embedded systems.

[BibT_eX]

[DOI]

Arslan Munir

Des. Autom. Embed. Syst., 2014

Dynamic Phase-Based Optimization of Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Analysis of cache tuner architectural layouts for multicore embedded systems.

[BibT_eX]

[DOI]

Marisha Rawlins

Proceedings of the IEEE 33rd International Performance Computing and Communications Conference, 2014

Thermal-aware phase-based tuning of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

2013

Exploiting dynamic phase distance mapping for phase-based tuning of embedded systems.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

2012

Dynamic phase-based tuning for embedded systems using phase distance mapping.

[BibT_eX]

[DOI]