Toshiyuki Oashi
According to our database1,
Toshiyuki Oashi
authored at least 5 papers
between 1994 and 2008.
Collaborative distances:
Collaborative distances:
Timeline
1994
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2008
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Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2008
A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations.
IEEE J. Solid State Circuits, 2008
A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues.
IEEE J. Solid State Circuits, 2008
2007
A 45nm Low-Standby-Power Embedded SRAM with Improved Immunity Against Process and Temperature Variations.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
1997
IEEE J. Solid State Circuits, 1997
1994
IEEE J. Solid State Circuits, November, 1994