Toshitsugu Sakamoto
According to our database1,
Toshitsugu Sakamoto
authored at least 21 papers
between 2005 and 2022.
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Bibliography
2022
IEICE Trans. Electron., October, 2022
IEEE J. Solid State Circuits, 2022
Enhanced Drain Current in Transient Mode due to Long Ionization Time of Shallow Impurities at 4 K in 65-nm bulk Cryo CMOS Transistors.
Proceedings of the Device Research Conference, 2022
2020
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020
33.3 Via-Switch FPGA: 65nm CMOS Implementation and Architecture Extension for Al Applications.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
2018
IEEE Embed. Syst. Lett., 2018
2017
2016
A 2× logic density Programmable Logic array using atom switch fully implemented with logic transistors at 40nm-node and beyond.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
2015
IEEE Micro, 2015
Sub-μW standby power, <18 μW/DMIPS@25MHz MCU with embedded atom-switch programmable logic and ROM.
Proceedings of the Symposium on VLSI Circuits, 2015
0.5-V Highly Power-Efficient Programmable Logic using Nonvolatile Configuration Switch in BEOL.
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Architecture of Reconfigurable-Logic Cell Array with Atom Switch: Cluster Size & Routing Fabrics (Abstract Only).
Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015
Proceedings of the 2015 IEEE Symposium in Low-Power and High-Speed Chips, 2015
2014
Low-power programmable-logic cell arrays using nonvolatile complementary atom switch.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014
2011
Programmable cell array using rewritable solid-electrolyte switch integrated in 90nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
2010
IEEE J. Solid State Circuits, 2010
2006
2005
IEEE J. Solid State Circuits, 2005