Toshiro Hiramoto
According to our database1,
Toshiro Hiramoto
authored at least 33 papers
between 1992 and 2024.
Collaborative distances:
Collaborative distances:
Timeline
1995
2000
2005
2010
2015
2020
0
1
2
3
4
5
1
3
2
1
1
1
2
2
2
1
1
1
1
4
3
2
1
2
1
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2024
Scaling Potential of Nanosheet Oxide Semiconductor FETs for Monolithic 3D Integration-ALD Material Engineering, High-Field Transport, Statistical Variability.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
Performance and Reliability of Nanosheet Oxide Semiconductor FETs with ALD-Grown InGaO for 3D Integration (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2024
2023
A Nanosheet Oxide Semiconductor FET Using ALD InGaOx Channel and InSnOx Electrode with Normally-off Operation, High Mobility and Reliability for 3D Integrated Devices.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
3-Layer stacked pixel-parallel CMOS image sensors using hybrid bonding of SOI wafers.
Proceedings of the Imaging Sensors and Systems 2022, online, January 15-26, 2022, 2022
2021
Proceedings of the 14th IEEE International Conference on ASIC, 2021
2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
Scalability Study on Ferroelectric-HfO2 Tunnel Junction Memory Based on Non-equilibrium Green Function Method.
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
Comprehensive Understanding of Negative Capacitance FET From the Perspective of Transient Ferroelectric Model.
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Proceedings of the 13th IEEE International Conference on ASIC, 2019
Triple-Layering Technology for Pixel-Parallel CMOS Image Sensors Developed by Hybrid Bonding of SOI Wafers.
Proceedings of the 2019 International 3D Systems Integration Conference (3DIC), 2019
2018
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
Quarter Video Graphics Array Full-Digital Image Sensing with Wide Dynamic Range and Linear Output Using Pixel-Wise 3D Integration.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Verification of the Injection Enhancement Effect in IGBTs by Measuring the Electron and Hole Currents Separately.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
Proceedings of the 12th IEEE International Conference on ASIC, 2017
2015
Nanoelectronics Research Gaps and Recommendations: A Report from the International Planning Working Group on Nanoelectronics (IPWGN) [Commentary].
IEEE Technol. Soc. Mag., 2015
Three-dimensional integrated circuits and stacked CMOS image sensors using direct bonding of SOI layers.
Proceedings of the 2015 International 3D Systems Integration Conference, 2015
2013
IEICE Trans. Electron., 2013
Experimental Demonstration of Post-Fabrication Self-Improvement of SRAM Cell Stability by High-Voltage Stress.
IEICE Trans. Electron., 2013
IEICE Trans. Electron., 2013
2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Statistical advantages of intrinsic channel fully depleted SOI MOSFETs over bulk MOSFETs.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
2010
Regional, National, and International Nanoelectronics Research Programs: Topical Concentration and Gaps.
Proc. IEEE, 2010
2007
Device Design of Nanoscale MOSFETs Considering the Suppression of Short Channel Effects and Characteristics Variations.
IEICE Trans. Electron., 2007
2006
IBM J. Res. Dev., 2006
2003
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model.
IEEE Trans. Very Large Scale Integr. Syst., 2003
2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
2000
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1994
IEEE J. Solid State Circuits, November, 1994
IEEE J. Solid State Circuits, April, 1994
1992
IEEE J. Solid State Circuits, April, 1992
IEEE J. Solid State Circuits, February, 1992