Toshio Takeshima

According to our database, Toshio Takeshima authored at least 3 papers between 1988 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1996

A 98 mm² die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell.

Masayoshi Ohkawa, Hiroshi Sugawara, Naoaki Sudo, Masaru Tsukiji, Ken-ichiro Nakagawa, Masato Kawata, Ken-ichi Oyama, Toshio Takeshima, Shuichi Ohya

IEEE J. Solid State Circuits, 1996

1990

A BIST scheme using microprogram ROM for large capacity memories.

Hiroki Koike, Toshio Takeshima, Masahide Takada

Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988

Voltage limiters for DRAMs with substrate-plate-electrode memory cells.

Toshio Takeshima, Masahide Takada, Toshiyuki Shimizu, Takuya Katoh, Mitsuru Sakamoto

IEEE J. Solid State Circuits, February, 1988