Toshio Takeshima

According to our database1, Toshio Takeshima authored at least 7 papers between 1988 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1988
1989
1990
1991
1992
1993
1994
1995
1996
0
1
2
3
4
1
1
1
2
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1996
A 98 mm<sup>2</sup> die size 3.3-V 64-Mb flash memory with FN-NOR type four-level cell.
IEEE J. Solid State Circuits, 1996

1993
A 30-ns 256-Mb DRAM with a multidivided array structure.
IEEE J. Solid State Circuits, November, 1993

1992
A 30-ns 64-Mb DRAM with built-in self-test and self-repair function.
IEEE J. Solid State Circuits, November, 1992

1990
A 5-ns 1-Mb ECL BiCMOS SRAM.
IEEE J. Solid State Circuits, October, 1990

A 55-ns 16-Mb DRAM with built-in self-test function using microprogram ROM.
IEEE J. Solid State Circuits, August, 1990

A BIST scheme using microprogram ROM for large capacity memories.
Proceedings of the Proceedings IEEE International Test Conference 1990, 1990

1988
Voltage limiters for DRAMs with substrate-plate-electrode memory cells.
IEEE J. Solid State Circuits, February, 1988


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