Toshinori Sato
Orcid: 0000-0001-5272-7533
According to our database1,
Toshinori Sato
authored at least 109 papers
between 1997 and 2024.
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Bibliography
2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks?- a Study of the Effects of "?" for Spoken Dialogue Systems -.
Proceedings of the 2024 Joint International Conference on Computational Linguistics, 2024
2023
Building a hospitable and reliable dialogue system for android robots: a scenario-based approach with large language models.
Adv. Robotics, November, 2023
PHALM: Building a Knowledge Graph from Scratch by Prompting Humans and a Language Model.
CoRR, 2023
Dialogue Systems Can Generate Appropriate Responses without the Use of Question Marks? - Investigation of the Effects of Question Marks on Dialogue Systems.
CoRR, 2023
Proceedings of the 24th Meeting of the Special Interest Group on Discourse and Dialogue, 2023
Bridging the Gap between Subword and Character Segmentation in Pretrained Language Models.
Proceedings of the 14th International Conference on Recent Advances in Natural Language Processing, 2023
Proceedings of the 37th Pacific Asia Conference on Language, 2023
Comparative Evaluation between Carry Prediction and Sign Error Correction in Approximate Addition.
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the 20th International SoC Design Conference, 2023
Proceedings of the International Symposium on Devices, Circuits and Systems, 2023
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023
2022
Proceedings of the 2022 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies: Student Research Workshop, 2022
Reducing Power Consumption using Approximate Encoding for CNN Accelerators at the Edge.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
Proceedings of the 4th International Symposium on Advanced Technologies and Applications in the Internet of Things (ATAIT 2022), 2022
2020
Exploiting Configurable Approximations for Tolerating Aging-induced Timing Violations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2020
IEICE Trans. Electron., 2020
Proceedings of the 5th International Conference on Computer and Communication Systems, 2020
2019
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019
IEICE Trans. Electron., 2019
Evaluation on Configurable Approximate Circuit for Aging-Induced Timing Violation Tolerance.
Proceedings of the 24th IEEE Pacific Rim International Symposium on Dependable Computing, 2019
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 2nd International Symposium on Devices, Circuits and Systems, 2019
Design of a Low-power and Small-area Approximate Multiplier using First the Approximate and then the Accurate Compression Method.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the IEEE 8th Global Conference on Consumer Electronics, 2019
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
Design and Analysis of A Low-Power High-Speed Accuracy-Controllable Approximate Multiplier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 19th International Symposium on Quality Electronic Design, 2018
Proceedings of the International SoC Design Conference, 2018
Approximate Adder Generation for Image Processing Using Convolutional Neural Network.
Proceedings of the International SoC Design Conference, 2018
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2013
Proceedings of the International Symposium on Quality Electronic Design, 2013
2012
J. Circuits Syst. Comput., 2012
Proceedings of the IEEE 18th Pacific Rim International Symposium on Dependable Computing, 2012
Proceedings of the International Symposium on Communications and Information Technologies, 2012
Proceedings of the 2012 International Conference on High Performance Computing & Simulation, 2012
Proceedings of the Euro-Par 2012 Parallel Processing - 18th International Conference, 2012
Proceedings of the Thirty-Fifth Australasian Computer Science Conference, 2012
2011
IEICE Trans. Electron., 2011
Proceedings of the International Conference on Complex, 2011
2010
Proceedings of the 16th IEEE Pacific Rim International Symposium on Dependable Computing, 2010
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010
2009
Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment.
IEICE Trans. Electron., 2009
A case for exploiting complex arithmetic circuits towards performance yield enhancement.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009
2008
IEICE Trans. Electron., 2008
IEICE Trans. Electron., 2008
Proceedings of the IEEE Symposium on Application Specific Processors, 2008
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008
2007
Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism.
Int. J. Comput. Their Appl., 2007
Proceedings of the 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 2007
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Proceedings of the Seventh International Conference on Computer and Information Technology (CIT 2007), 2007
2006
SIGARCH Comput. Archit. News, 2006
J. Embed. Comput., 2006
Proceedings of the 12th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2006), 2006
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006
2005
Profiling with Helper Threads.
Proceedings of the IASTED International Conference on Parallel and Distributed Computing and Networks, 2005
Proceedings of the High-Performance Computing - 6th International Symposium, 2005
Exploiting Trivial Computation in Dependable Processors.
Proceedings of the 20th International Conference on Computers and Their Applications, 2005
2004
A leakage-energy-reduction technique for highly-associative caches in embedded systems.
SIGARCH Comput. Archit. News, 2004
Proceedings of the SPAA 2004: Proceedings of the Sixteenth Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2004
Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture.
Proceedings of the Intenational Symposium on Information and Communication Technologies, 2004
Proceedings of the 24th International Conference on Distributed Computing Systems Workshops (ICDCS 2004 Workshops), 2004
Proceedings of the Embedded and Ubiquitous Computing, 2004
A static and dynamic energy reduction technique for I-cache and BTB in embedded processors.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004
2003
SIGARCH Comput. Archit. News, 2003
Combining variable latency pipeline with instruction reuse for execution latency reduction.
Syst. Comput. Jpn., 2003
Proceedings of the Integrated Circuit and System Design, 2003
Proceedings of the 2003 IEEE International Conference on Field-Programmable Technology, 2003
Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003
Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation.
Proceedings of the 16th International Conference on Computer Applications in Industry and Engineering, 2003
2002
Evaluating the impact of reissued instructions on data speculative processor performance.
Microprocess. Microsystems, 2002
J. Inf. Sci. Eng., 2002
The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2002
Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002
Proceedings of the High Performance Computing, 4th International Symposium, 2002
Proceedings of the 2002 Euromicro Symposium on Digital Systems Design (DSD 2002), 2002
2001
Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications.
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001
Proceedings of the 2001 International Conference on Parallel Processing, 2001
Proceedings of the High-Performance Computing and Networking, 9th International Conference, 2001
Proceedings of the Euro-Par 2001: Parallel Processing, 2001
Tolerating Transient Faults through an Instruction Reissue Mechanism.
Proceedings of the ISCA 14th International Conference on Parallel and Distributed Computing Systems, 2001
2000
2.44-GFLOPS 300-MHz floating-point vector-processing unit for high-performance 3D graphics computing.
IEEE J. Solid State Circuits, 2000
Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism.
J. Syst. Archit., 2000
The KIT COSMOS Processor: Introducing CONDOR.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000
Proceedings of the 5th International Symposium on Parallel Architectures, 2000
Proceedings of the 14th international conference on Supercomputing, 2000
Proceedings of the 2000 International Conference on Parallel Processing, 2000
Proceedings of ASP-DAC 2000, 2000
1999
Int. J. High Speed Comput., 1999
Proceedings of the High Performance Computing, Second International Symposium, 1999
Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure.
Proceedings of the Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31, 1999
A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism.
Proceedings of the 25th EUROMICRO '99 Conference, 1999
1998
Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
1997
Proceedings of the High Performance Computing, International Symposium, 1997