Toshinori Hosokawa

According to our database, Toshinori Hosokawa authored at least 51 papers between 1993 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

CRLock: A SAT and FALL Attacks Resistant Logic Locking Method for Controller at Register Transfer Level.

Masayoshi Yoshimura, Atsuya Tsujikawa, Toshinori Hosokawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2024

2023

An Evaluation of Estimated Field Random Testability for Data Paths at Register Transfer Level Using Status Signal Sequences Based on k-Consecutive State Transitions for Field Testing.

Yudai Toyooka, Haruki Watanabe, Toshinori Hosokawa, Masayoshi Yoshimura

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

An Estimation Method of Defect Types Using Artificial Neural Networks and Fault Detection Information.

Natsuki Ota, Toshinori Hosokawa, Koji Yamazaki, Yukari Yamauchi, Masayuki Arai

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

A Block Partitioning Method for Region Exhaustive Test to Reduce the Number of Test Patterns and Improve Gate Exhaustive Fault Coverage.

Momona Mizota, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

An Evaluation of a Testability Measure for State Assignment to Estimate Transition Fault Coverage for Controllers.

Toshinori Hosokawa, Kyohei Iizuka, Masayoshi Yoshimura

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2023

2022

CRLock: A SAT and FALL Attacks Resistant Logic Locking Method at Register Transfer Level.

Masayoshi Yoshimura, Atsuya Tsujikawa, Hiroshi Yamazaki, Toshinori Hosokawa

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2022

2020

Universal Testing for Linear Feed-Forward/Feedback Shift Registers.

Hideo Fujiwara, Katsuya Fujiwara, Toshinori Hosokawa

IEICE Trans. Inf. Syst., 2020

A Test Sensitization State Compaction Method on Controller Augmentation.

Yuki Ikegaya, Toshinori Hosokawa, Yuta Ishiyama, Hiroshi Yamazaki

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method.

Toshinori Hosokawa, Kenichiro Misawa, Hiroshi Yamazaki, Masayoshi Yoshimura, Masayuki Arai

Proceedings of the 26th IEEE International Symposium on On-Line Testing and Robust System Design, 2020

A Multiple Target Test Generation Method for Gate-Exhaustive Faults to Reduce the Number of Test Patterns Using Partial MaxSAT.

Ryuki Asami, Toshinori Hosokawa, Masayoshi Yoshimura, Masayuki Arai

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

A Controller Augmentation Method to Improve Transition Fault Coverage for RTL Data-Paths.

Yuki Takeuchi, Toshinori Hosokawa, Hiroshi Yamazaki, Masayoshi Yoshimura

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A Test Generation Method Based on k-Cycle Testing for Finite State Machines.

Yuya Kinoshita, Toshinori Hosokawa, Hideo Fujiwara

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A Design for Testability Method for k-Cycle Capture Test Generation.

Yuta Ishiyama, Toshinori Hosokawa, Hiroshi Yamazaki

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

A State Assignment Method to Improve Transition Fault Coverage for Controllers.

Masayoshi Yoshimura, Yuki Takeuchi, Hiroshi Yamazaki, Toshinori Hosokawa

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

A Low Capture Power Oriented X-filling Method Using Partial MaxSAT Iteratively.

Toshinori Hosokawa, Hiroshi Yamazaki, Kenichiro Misawa, Masayoshi Yoshimura, Yuki Hirama, Masavuki Arai

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

2018

A Capture Safe Static Test Compaction Method Based on Don't Cares.

Sayuri Ochi, Hiroshi Yamazaki, Toshinori Hosokawa, Masayoshi Yoshimura

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

A Test Register Assignment Method Based on Controller Augmentation to Reduce the Number of Test Patterns.

Toshinori Hosokawa, Hiroshi Yamazaki, Shun Takeda, Masayoshi Yoshimura

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

A Sequentially Untestable Fault Identification Method Based on n-Bit State Cube Justification.

Toshinori Hosokawa, Morito Niseki, Masayoshi Yoshimura, Hiroshi Yamazaki, Masayuki Arai, Hiroyuki Yotsuyanagi, Masaki Hashizume

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

2017

A Don't Care Filling Method for Low Capture Power based on Correlation of FF Transitions Using SAT.

Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

A Low Capture Power Test Generation Method Based on Capture Safe Test Vector Manipulation.

Toshinori Hosokawa, Atsushi Hirai, Yukari Yamauchi, Masayuki Arai

IEICE Trans. Inf. Syst., 2017

A Hardware Trojan Circuit Detection Method Using Activation Sequence Generations.

Masayoshi Yoshimura, Tomohiro Bouyashiki, Toshinori Hosokawa

Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

A Diagnostic Fault Simulation Method for a Single Universal Logical Fault Model.

Toshinori Hosokawa, Hideyuki Takano, Hiroshi Yamazaki, Koji Yamazaki

Proceedings of the 22nd IEEE Pacific Rim International Symposium on Dependable Computing, 2017

Controller augmentation and test point insertion at RTL for concurrent operational unit testing.

Toshinori Hosokawa, Shun Takeda, Hiroshi Yamazaki, Masayoshi Yoshimura

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

A dynamic test compaction method on low power test generation based on capture safe test vectors.

Toshinori Hosokawa, Atsushi Hirai, Hiroshi Yamazaki, Masayuki Arai

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2017

2016

A scheduling method for hierarchical testability based on test environment generation results.

Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara

Proceedings of the 21th IEEE European Test Symposium, 2016

2015

A low capture power test generation method using capture safe test vectors.

Atsushi Hirai, Yukari Yamauchi, Toshinori Hosokawa, Masayuki Arai

Proceedings of the 20th IEEE European Test Symposium, 2015

A Don't Care Filling Method to Reduce Capture Power Based on Correlation of FF Transitions.

Masayoshi Yoshimura, Yoshiyasu Takahashi, Hiroshi Yamazaki, Toshinori Hosokawa

Proceedings of the 24th IEEE Asian Test Symposium, 2015

A Test Generation Method for Data Paths Using Easily Testable Functional Time Expansion Models and Controller Augmentation.

Tetsuya Masuda, Jun Nishimaki, Toshinori Hosokawa, Hideo Fujiwara

Proceedings of the 24th IEEE Asian Test Symposium, 2015

2013

A Test Compaction Oriented Don't Care Identification Method Based on X-bit Distribution.

Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura

IEICE Trans. Inf. Syst., 2013

A smart Trojan circuit and smart attack method in AES encryption circuits.

Masayoshi Yoshimura, Amy Ogita, Toshinori Hosokawa

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

A don't care identification method for test compaction.

Hiroshi Yamazaki, Motohiro Wakazono, Toshinori Hosokawa, Masayoshi Yoshimura

Proceedings of the 16th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2013

2010

A Fault Dependent Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint.

Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2010

Evaluation of transition untestable faults using a multi-cycle capture test generation method.

Masayoshi Yoshimura, Hiroshi Ogawa, Toshinori Hosokawa, Koji Yamazaki

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2008

A Test Generation Method for State-Observable FSMs to Increase Defect Coverage under the Test Length Constraint.

Ryoichi Inoue, Toshinori Hosokawa, Hideo Fujiwara

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

Fault-dependent/independent Test Generation Methods for State Observable FSMs.

Toshinori Hosokawa, Ryoichi Inoue, Hideo Fujiwara

Proceedings of the 16th Asian Test Symposium, 2007

2005

An Effective Design for Hierarchical Test Generation Based on Strong Testability.

Hideyuki Ichihara, Tomoo Inoue, Naoki Okamoto, Toshinori Hosokawa, Hideo Fujiwara

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004

A DFT Selection Method for Reducing Test Application Time of System-on-Chips.

Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara

IEICE Trans. Inf. Syst., 2004

2003

A Method of Test Plan Grouping to Shorten Test Length for RTL Data Paths under a Test Controller Area Constraint.

Toshinori Hosokawa, Hiroshi Date, Masahide Miyazaki, Michiaki Muraoka, Hideo Fujiwara

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

VCore-based design methodology.

Michiaki Muraoka, Hideyuki Hamada, Hiroaki Nishi, Toshihiko Tada, Yoichi Onishi, Toshinori Hosokawa, Kenji Yoshida

Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002

Test sequence compaction methods for acyclic sequential circuits using a time expansion model.

Toshinori Hosokawa, Tomoo Inoue, Toshihiro Hiraoka, Hideo Fujiwara

Syst. Comput. Jpn., 2002

A Test Generation Method Using a Compacted Test Table and a Test Generation Method Using a Compacted Test Plan Table for RTL Data Path Circuits.

Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka

Proceedings of the 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April, 2002

A Test Point Insertion Method to Reduce the Number of Test Patterns.

Masayoshi Yoshimura, Toshinori Hosokawa, Mitsuyasu Ohta

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A State Reduction Method for Non-Scan Based FSM Testing with Don't Care Inputs Identification Technique.

Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

A SoC Test Strategy Based on a Non-Scan DFT Method.

Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Design for testability strategies using full/partial scan designs and test point insertions to reduce test application times.

Toshinori Hosokawa, Masayoshi Yoshimura, Mitsuyasu Ohta

Proceedings of ASP-DAC 2001, 2001

1999

Static and Dynamic Test Sequence Compaction Methods for Acyclic Sequential Circuits Using a Time Expansion Model.

Toshinori Hosokawa, Toshihiro Hiraoka, Tomoo Inoue, Hideo Fujiwara

Proceedings of the 8th Asian Test Symposium (ATS '99), 1999

1998

An Optimal Time Expansion Model Based on Combinational ATPG for RT level Circuits.

Tomoo Inoue, Toshinori Hosokawa, Takahiro Mihara, Hideo Fujiwara

Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

1997

A Partial Scan Design Method Based on n-Fold Line-up Structures.

Toshinori Hosokawa, Toshihiro Hiraoka, Mitsuyasu Ohta, Michiaki Muraoka, Shigeo Kuninobu

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1996

A Design for testability Method Using RTL Partitioning.

Toshinori Hosokawa, Kenichi Kawaguchi, Mitsuyasu Ohta, Michiaki Muraoka

Proceedings of the 5th Asian Test Symposium (ATS '96), 1996

1995

Design for testability using register-transfer level partial scan selection.

Akira Motohara, Sadami Takeoka, Toshinori Hosokawa, Mitsuyasu Ohta, Yuji Takai, Michihiro Matsumoto, Michiaki Muraoka

Proceedings of the 1995 Conference on Asia Pacific Design Automation, Makuhari, Massa, Chiba, Japan, August 29, 1995

1993

A State Traversal Algorithm Using a State Covariance Matrix.

Akira Motohara, Toshinori Hosokawa, Michiaki Muraoka, Hidetsugu Maekawa, Kazuhiro Kayashima, Yasuharu Shimeki, Seichi Shin

Proceedings of the 30th Design Automation Conference. Dallas, 1993