Toshinobu Shinbo

According to our database1, Toshinobu Shinbo authored at least 2 papers between 1995 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996

1995
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.
IEEE J. Solid State Circuits, March, 1995


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