Toshinobu Shinbo

According to our database1, Toshinobu Shinbo authored at least 3 papers between 1993 and 1996.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996

1995
A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.
IEEE J. Solid State Circuits, March, 1995

1993
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic.
IEEE J. Solid State Circuits, November, 1993


  Loading...