Toshinobu Shinbo

According to our database, Toshinobu Shinbo authored at least 3 papers between 1993 and 1996.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1996

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.

Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure

IEEE J. Solid State Circuits, 1996

1995

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.

Norio Ohkubo, Makoto Suzuki, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

IEEE J. Solid State Circuits, March, 1995

1993

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic.

Makoto Suzuki, Norio Ohkubo, Toshinobu Shinbo, Toshiaki Yamanaka, Akihiro Shimizu, Katsuro Sasaki, Yoshinobu Nakagome

IEEE J. Solid State Circuits, November, 1993