Toshinobu Shinbo
According to our database1,
Toshinobu Shinbo
authored at least 3 papers
between 1993 and 1996.
Collaborative distances:
Collaborative distances:
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Bibliography
1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996
1995
IEEE J. Solid State Circuits, March, 1995
1993
IEEE J. Solid State Circuits, November, 1993