Toshinobu Ono

According to our database, Toshinobu Ono authored at least 4 papers between 1991 and 2001.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2001

An Application of Partial Scan Techniques to a High-End System LSI Design.

Toshinobu Ono, Akira Kozawa, Takashi Kimura, Yoshihiro Konno, Koji Saga

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

1997

Integrated and Automated Design-for-Testability Implementation for Cell-Based ICs.

Toshinobu Ono, Kazuo Wakui, Hitoshi Hikima, Yoshiyuki Nakamura, Masaaki Yoshida

Proceedings of the 6th Asian Test Symposium (ATS '97), 17-18 November 1997, 1997

1994

Selecting partial scan flip-flops for circuit partitioning.

Toshinobu Ono

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

1991

A Test Generation Method for Sequential Circuits Based on Maximum Utilization of Internal States.

Toshinobu Ono, Masaaki Yoshida

Proceedings of the Proceedings IEEE International Test Conference 1991, 1991