Toshinari Takayanagi

According to our database, Toshinari Takayanagi authored at least 8 papers between 1989 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2007

A 25W SoC with Dual 2GHz Power Cores and Integrated Memory and I/O Subsystems.

Zongjian Chen, Priya Ananthanarayanan, Sukalp Biswas, Brian Campbell, Hao Chen, Shaishav Desai, Dominic Go, Rajat Goel, Vincent von Kaenel, Jason Kassoff, Fabian Klass, Weichun Ku, Tony Li, Jonathon Lin, Khurram Malik, Anup Mehta, Daniel Murray, Eric Shiu, Chris Shuler, Sribalan Santhanam, Greg Scott, Junji Sugisawa, Toshinari Takayanagi, Honkai John Tarn, Pradeep Trivedi, James Wang, Ricky Wen, John Yong

Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

Dual True Random Number Generators for Cryptographic Applications Embedded on a 200 Million Device Dual CPU SoC.

Vincent von Kaenel, Toshinari Takayanagi

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2005

A dual-core 64-bit ultraSPARC microprocessor for dense server applications.

Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Howard Levy, Ha Pham, Jinseung Son, Nathan Moon, Dina Bistry, Umesh Nair, Mandeep Singh, Vikas Mathur, Ana Sonia Leon

IEEE J. Solid State Circuits, 2005

2004

A dual-core 64b ultraSPARC microprocessor for dense server applications.

Toshinari Takayanagi, Jinuk Luke Shin, Bruce Petrick, Jeffrey Y. Su, Ana Sonia Leon

Proceedings of the 41th Design Automation Conference, 2004

2001

A bitline leakage compensation scheme for low-voltage SRAMs.

Ken-ichi Agawa, Hiroyuki Hara, Toshinari Takayanagi, Tadahiro Kuroda

IEEE J. Solid State Circuits, 2001

2000

A 60-MHz 240-mW MPEG-4 videophone LSI with 16-Mb embedded DRAM.

Masafumi Takahashi, Tsuyoshi Nishikawa, Mototsugu Hamada, Toshinari Takayanagi, Hideho Arakida, Noriaki Machida, Hideaki Yamamoto, Toshihide Fujiyoshi, Yoko Ohashi, Osamu Yamagishi, Tatsuo Samata, Atsushi Asano, Toshihiro Terazawa, Kenji Ohmori, Yoshinori Watanabe, Hiroki Nakamura, Shigenobu Minami, Tadahiro Kuroda, Tohru Furuyama

IEEE J. Solid State Circuits, 2000

1990

A 9-ns HIT-delay 32-kbyte cache macro for high-speed RISC.

Kazutaka Nogami, Takayasu Sakurai, Kazuhiro Sawada, Kenji Sakaue, Yuichi Miyazawa, Shinichi Tanaka, Ypocjo Hiruta, Katsuto Katoh, Toshinari Takayanagi, Tsukasa Shirotori, Yasuo Itoh, Masanori Uchida, Tetsuya Iizuka

IEEE J. Solid State Circuits, February, 1990

1989

A 32 kbyte integrated cache memory.

Kazuhiro Sawada, Takayasu Sakurai, Kazutaka Nogami, Tsukasa Shirotori, Toshinari Takayanagi, Tetsuya Iizuka, Takeo Maeda, Jinichi Matsunaga, Hiromichi Fuji, Kenji Maeguchi, Kiyoshi Kobayashi, Tomoyuki Ando, Yoshiki Hayakashi, Akio Miyoshi, Kazuyuki Sato

IEEE J. Solid State Circuits, August, 1989