Toshimasa Namekawa

According to our database, Toshimasa Namekawa authored at least 3 papers between 2000 and 2004.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2004

Post-Packaging Auto Repair Techniques for Fast Row Cycle Embedded DRAM.

Osamu Wada, Toshimasa Namekawa, Hiroshi Ito, Atsushi Nakayama, Shuso Fujii

Proceedings of the Proceedings 2004 International Test Conference (ITC 2004), 2004

Pure CMOS one-time programmable memory using gate-ox anti-fuse.

Hiroshi Ito, Toshimasa Namekawa

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2000

Dynamically shift-switched dataline redundancy suitable for DRAM macro with wide data bus.

Toshimasa Namekawa, Shinji Miyano, Ryo Fukuda, Ryo Haga, Osamu Wada, Hironori Banba, Satoru Takeda, Kazuhiro Suda, Kenichiro Mimoto, Satoshi Yamaguchi, Tsutomu Ohkubo, Hiroshi Takato, Kenji Numata

IEEE J. Solid State Circuits, 2000