Toshiki Nakamura
Orcid: 0000-0002-0746-4807
According to our database1,
Toshiki Nakamura
authored at least 15 papers
between 2015 and 2021.
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Bibliography
2021
CoRR, 2021
MIMII Due: Sound Dataset for Malfunctioning Industrial Machine Investigation and Inspection with Domain Shifts Due to Changes in Operational and Environmental Conditions.
Proceedings of the IEEE Workshop on Applications of Signal Processing to Audio and Acoustics, 2021
2020
Description and Discussion on DCASE2020 Challenge Task2: Unsupervised Anomalous Sound Detection for Machine Condition Monitoring.
Proceedings of 5th the Workshop on Detection and Classification of Acoustic Scenes and Events 2020 (DCASE 2020), 2020
2019
Adaptive Artificial Neural Network-Coupled LDPC ECC as Universal Solution for 3-D and 2-D, Charge-Trap and Floating-Gate NAND Flash Memories.
IEEE J. Solid State Circuits, 2019
3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition.
IEEE J. Solid State Circuits, 2019
Proceedings of the 2019 International Conference on Document Analysis and Recognition, 2019
Privacy-Aware Data-Lifetime Control NAND Flash System for Right to be Forgotten with In-3D Vertical Cell Processing.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
Layer-by-layer Adaptively Optimized ECC of NAND flash-based SSD Storing Convolutional Neural Network Weight for Scene Recognition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Data-Aware Partial ECC with Data Modulation of ReRAM with Non-volatile In-memory Computing for Image Recognition with Deep Neural Network.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Error elimination ECC by horizontal error detection and vertical-LDPC ECC to increase data-retention time by 230% and acceptable bit-error rate by 90% for 3D-NAND flash SSDs.
Proceedings of the IEEE International Reliability Physics Symposium, 2018
Endurance-based Dynamic VTHDistribution Shaping of 3D-TLC NAND Flash Memories to Suppress Both Lateral Charge Migration and Vertical Charge De-trap and Increase Data-retention Time by 2.7x.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
9.1x Error acceptable adaptive artificial neural network coupled LDPC ECC for charge-trap and floating-gate 3D-NAND flash memories.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
Proceedings of the 14th IAPR International Conference on Document Analysis and Recognition, 2017
12× bit-error acceptable, 300× extended data-retention time, value-aware SSD with vertical 3D-TLC NAND flash memories for image recognition.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2015
An on-chip, electricity-free and single-layer pressure sensor for microfluidic applications.
Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015