Toshiki Kanamoto
Orcid: 0000-0002-6326-6960
According to our database1,
Toshiki Kanamoto
authored at least 41 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
Proceedings of the 13th IEEE Global Conference on Consumer Electronics, 2024
2023
Bayesian neural network based inductance calculations of wireless power transfer systems.
IEICE Electron. Express, 2023
IEICE Electron. Express, 2023
IEICE Electron. Express, 2023
IEICE Electron. Express, 2023
Ultra-Low-Latency Video Coding with Reduced Frame Memory Structure for 4K/8K High-Resolution Video.
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023
Proceedings of the 12th IEEE Global Conference on Consumer Electronics, 2023
2022
IEICE Electron. Express, 2022
IEICE Electron. Express, 2022
Enhanced laser trimming of thin film resistors dedicated to snubber for high power IGBT modules.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Deep Neural Network Based Inductance Calculations of Wireless Power Transfer Systems.
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022
Proceedings of the 11th IEEE Global Conference on Consumer Electronics, 2022
2021
IEICE Electron. Express, 2021
A Virtual Optical Holographic Encryption System Using Expanded Diffie-Hellman Algorithm.
IEEE Access, 2021
2020
IEICE Electron. Express, 2020
A simple yet precise capacitance estimation method for on-chip power delivery network towards EMC analysis.
IEICE Electron. Express, 2020
2019
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 25th IEEE International Symposium on Asynchronous Circuits and Systems, 2019
2018
IEICE Electron. Express, 2018
2015
IEICE Electron. Express, 2015
2014
Resistivity-based modeling of substrate non-uniformity for low-resistivity substrate.
IEICE Electron. Express, 2014
2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
2010
Exhaustive and Systematic Accuracy Verification and Enhancement of STI Stress Compact Model for General Realistic Layout Patterns.
IEICE Trans. Electron., 2010
A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010
IEICE Trans. Electron., 2010
2009
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009
2008
A Parallel Method to Extract Critical Areas of Net Pairs for Diagnosing Bridge Faults.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008
2007
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
2005
A Practical Approach for Efficiently Extracting Interconnect Capacitances with Floating Dummy Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Efficient Dummy Filling Methods to Reduce Interconnect Capacitance and Number of Dummy Metal Fills.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005
2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
1999