Toshikazu Suzuki
According to our database1,
Toshikazu Suzuki
authored at least 26 papers
between 1993 and 2014.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2014
IEEE J. Solid State Circuits, 2014
2013
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.
IEEE J. Solid State Circuits, 2013
A 6T-SRAM With a Post-Process Electron Injection Scheme That Pinpoints and Simultaneously Repairs Disturb Fails for 57% Less Read Delay and 31% Less Read Energy.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
2012
IEICE Trans. Electron., 2012
IEICE Electron. Express, 2012
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.
Proceedings of the Symposium on VLSI Circuits, 2012
A 6T SRAM with a carrier-injection scheme to pinpoint and repair fails that achieves 57% faster read and 31% lower read energy.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
A 40-nm 256-Kb 0.6-V operation half-select resilient 8T SRAM with sequential writing technique enabling 367-mV VDDmin reduction.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
A 40-nm 256-Kb Sub-10 pJ/Access 8t SRAM with read bitline amplitude limiting (RBAL) scheme.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
60% Cycle time acceleration, 55% energy reduction, 32Kbit SRAM by auto-selective boost (ASB) scheme for slow memory cells in random variations.
Proceedings of the 38th European Solid-State Circuit conference, 2012
2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
Energy efficiency degradation caused by random variation in low-voltage SRAM and 26% energy reduction by Bitline Amplitude Limiting (BAL) scheme.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2008
A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses.
IEEE J. Solid State Circuits, 2008
2007
A 1R/1W SRAM Cell Design to Keep Cell Current and Area Saving against Simultaneous Read/Write Disturbed Accesses.
IEICE Trans. Electron., 2007
A Stable SRAM Mitigating Cell-Margin Asymmetricity with A Disturb-Free Biasing Scheme.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
A sub-0.5-V operating embedded SRAM featuring a multi-bit-error-immune hidden-ECC scheme.
IEEE J. Solid State Circuits, 2006
A Differential Cell Terminal Biasing Scheme Enabling a Stable Write Operation against a Large Random Threshold Voltage (<i>V</i><sub>th</sub>) Variation.
IEICE Trans. Electron., 2006
2005
0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier.
IEICE Trans. Electron., 2005
2004
A 90-nm low-power 32-kB embedded SRAM with gate leakage suppression circuit for mobile applications.
IEEE J. Solid State Circuits, 2004
2003
AtelierM: a physically based interactive system for creating traditional marbling textures.
Proceedings of the 1st International Conference on Computer Graphics and Interactive Techniques in Australasia and Southeast Asia 2003, 2003
2001
Simulating Marbling with Computer Graphics.
Proceedings of the IASTED International Conference on Visualization, 2001
1994
1993
IEEE J. Solid State Circuits, November, 1993