Toshikazu Sekine

IEICE Electron. Express, 2019

2017

Operational amplifier based LC resonant circuit for adiabatic logic.

[BibT_eX]

[DOI]

Mei Han

Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017

Low power Adiabatic Logic based on 2PC2AL.

[BibT_eX]

[DOI]

Mei Han

Proceedings of the 2017 IEEE International Conference on IC Design and Technology, 2017

Generalized indirect S-parameter measurement method of n-ports circuit using T-parameter of (m, n)-ports fixture.

[BibT_eX]

[DOI]

Yuya Kojima

Proceedings of the 2017 European Conference on Circuit Theory and Design, 2017

2015

Low-power secure S-box circuit using charge-sharing symmetric adiabatic logic for advanced encryption standard hardware design.

[BibT_eX]

[DOI]

IET Circuits Devices Syst., 2015

SPICE model of memristive device using Tukey window function.

[BibT_eX]

[DOI]

Michio Yokoyama

IEICE Electron. Express, 2015

Two phase clocked subthreshold adiabatic logic circuit.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2015

A 4×4-bit multiplier LSI implementation of two phase clocking subthreshold adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE 13th International New Circuits and Systems Conference, 2015

An improved estimation method of 4 port S-parameters with 2 port measurements.

[BibT_eX]

[DOI]

Proceedings of the European Conference on Circuit Theory and Design, 2015

2014

Process variation verification of low-power secure CSSAL AES S-box circuit.

[BibT_eX]

[DOI]

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

An LSI implementation of a bit-parallel cellular multiplier over GF(2<sup>4</sup>) using secure charge-sharing symmetric adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Two phase clocking subthreshold adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Power dissipation analysis of memristor for low power integrated circuit applications.

[BibT_eX]

[DOI]

Haruki Ogata

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Effectiveness of dual-rail CSSAL against power analysis attack under CMOS process variation.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

Skew tolerance analysis and layout design of 4×4 multiplier using two phase clocking subthreshold adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Charge-sharing symmetric adiabatic logic in countermeasure against power analysis attacks at cell level.

[BibT_eX]

[DOI]

Microelectron. J., 2013

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks.

[BibT_eX]

[DOI]

Proceedings of the 36th International Conference on Telecommunications and Signal Processing, 2013

DPA resistance of charge-sharing symmetric adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Low power secure CSSAL bit-parallel multiplier over GF(2<sup>4</sup>) in 0.18μm CMOS technology.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

An estimation method for the 3 port S-parameters with 1 port measurements.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

2012

LSI implementation of a low-power 4×4-bit array two-phase clocked adiabatic static CMOS logic multiplier.

[BibT_eX]

[DOI]

Nazrul Anuar Nayan

Microelectron. J., 2012

Power-saving analysis of adiabatic logic in subthreshold region.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2012

A low-power sense amplifier for adiabatic memory using memristor.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2PCDAL: Two-phase clocking dual-rail adiabatic logic.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

Resistance against power analysis attacks on adiabatic dynamic and adiabatic differential logics for smart card.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

Low-power adiabatic SRAM.

[BibT_eX]

[DOI]

Hides Jamima

Proceedings of the International Symposium on Intelligent Signal Processing and Communications Systems, 2011

2010

4×4-bit array two phase clocked adiabatic static CMOS logic multiplier with new XOR.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010

2009

Two phase clocked adiabatic static CMOS logic.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Symposium on System-on-Chip, 2009

A new horizontal and vertical common subexpression elimination method for multiple constant multiplication.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

Fundamental logics based on two phase clocked adiabatic static CMOS logic.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Conference on Electronics, 2009

4-bit ripple carry adder of two-phase clocked adiabatic static CMOS logic: A comparison with static CMOS.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2007

VLSI Implementation of a 4 x 4-bit Multiplier in a Two Phase Drive Adiabatic Dynamic CMOS Logic.

[BibT_eX]

[DOI]

Michio Yokoyama

IEICE Trans. Electron., 2007

A 70 MHz Multiplierless FIR Hilbert Transformer in 0.35 µm Standard CMOS Library.

[BibT_eX]

[DOI]