Toshihiro Katashita
Orcid: 0000-0002-0723-6564
According to our database1,
Toshihiro Katashita
authored at least 25 papers
between 2006 and 2024.
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Bibliography
2024
Multiplication-Free Lookup-Based CNN Accelerator Using Residual Vector Quantization and Its FPGA Implementation.
IEEE Access, 2024
FPGA Implementation of Physically Unclonable Functions Based on Multi-threshold Delay Time Measurement Method to Mitigate Modeling Attacks.
Proceedings of the Applied Cryptography and Network Security Workshops, 2024
2021
Evaluation of Side-Channel Leakage Simulation by Using EMC Macro-Model of Cryptographic Devices.
IEICE Trans. Commun., 2021
2020
Implementation of pseudo-linear feedback shift register-based physical unclonable functions on silicon and sufficient Challenge-Response pair acquisition using Built-In Self-Test before shipping.
Integr., 2020
2019
A Deep Learning Attack Countermeasure with Intentional Noise for a PUF-Based Authentication Scheme.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2019
2018
Development of an Evaluation Platform and Performance Experimentation of Flex Power FPGA Device.
IEICE Trans. Inf. Syst., 2018
2017
Proceedings of the IEEE 6th Global Conference on Consumer Electronics, 2017
2015
A Silicon-Level Countermeasure Against Fault Sensitivity Analysis and Its Evaluation.
IEEE Trans. Very Large Scale Integr. Syst., 2015
2014
Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays.
J. Inf. Process., 2014
Power Noise Measurements of Cryptographic VLSI Circuits Regarding Side-Channel Information Leakage.
IEICE Trans. Electron., 2014
2013
Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption.
IEICE Trans. Inf. Syst., 2013
A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013
Energy and area saving effect of Dynamic Partial Reconfiguration on a 28-nm process FPGA.
Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013
2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
Circuit Simulation for Fault Sensitivity Analysis and Its Application to Cryptographic LSI.
Proceedings of the 2012 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2012
2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
A fast power current analysis methodology using capacitor charging model for side channel attack evaluation.
Proceedings of the HOST 2011, 2011
2010
Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs.
Proceedings of the ReConFig'10: 2010 International Conference on Reconfigurable Computing and FPGAs, 2010
2009
Proceedings of the 19th European Conference on Circuit Theory and Design, 2009
2008
Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008
2007
IEICE Trans. Inf. Syst., 2007
2006
A Method of Generating Highly Efficient String Matching Circuit for Intrusion Detection.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006