Toshifumi Nakatani
According to our database1,
Toshifumi Nakatani
authored at least 8 papers
between 2005 and 2022.
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Bibliography
2022
A 29-dBm, 34% PAE E-Band Dual-Input Doherty Power Amplifier Using 40-nm GaN Technology.
Proceedings of the 2022 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2022
2017
A 1-3 GHz Delta-Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI.
IEEE J. Solid State Circuits, 2017
2013
A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage.
IEEE J. Solid State Circuits, 2013
A fully integrated 60GHz CMOS transceiver chipset based on WiGig/IEEE802.11ad with built-in self calibration for mobile applications.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
2012
Digitally-Controlled Polar Transmitter Using a Watt-Class Current-Mode Class-D CMOS Power Amplifier and Guanella Reverse Balun for Handset Applications.
IEEE J. Solid State Circuits, 2012
2008
A Low Distortion and Low Noise Differential Amplifier Suitable for 3G LTE Applications Using the Even- and Odd-Mode Impedance Differences of a Bias Circuit.
IEICE Trans. Electron., 2008
2007
IM3 Cancellation Method Using Current Feedback Suitable for a Multi-Stage RFIC Amplifier.
IEICE Trans. Electron., 2007
2005
A New Design Concept for Balanced-Type SAW Filters Using a Common-Mode Signal Suppression Circuit.
IEICE Trans. Electron., 2005