Toshiaki Yamanaka

According to our database1, Toshiaki Yamanaka authored at least 15 papers between 1989 and 2013.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1990
1995
2000
2005
2010
0
1
2
3
4
5
4
1
2
3
3
1
1

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2013
Accuracy assessment of kinect body tracker in instant posturography for balance disorders.
Proceedings of the 7th International Symposium on Medical Information and Communication Technology, 2013

1995
A 300-MHz 4-Mb wave-pipeline CMOS SRAM using a multiphase PLL.
IEEE J. Solid State Circuits, November, 1995

A 2.6-ns wave-pipelined CMOS SRAM with dual-sensing-latch circuits.
IEEE J. Solid State Circuits, April, 1995

A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current sense amplifiers.
IEEE J. Solid State Circuits, April, 1995

A 4.4 ns CMOS 54⨉54-b multiplier using pass-transistor multiplexer.
IEEE J. Solid State Circuits, March, 1995

1994
A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers.
IEEE J. Solid State Circuits, April, 1994

1993
A 1.5-ns 32-b CMOS ALU in double pass-transistor logic.
IEEE J. Solid State Circuits, November, 1993

A 16-Mb CMOS SRAM with a 2.3- mu m/sup 2/ single-bit-line memory cell.
IEEE J. Solid State Circuits, November, 1993

1992
A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier.
IEEE J. Solid State Circuits, November, 1992

A 1-V TFT-load SRAM using a two-step word-voltage method.
IEEE J. Solid State Circuits, November, 1992

A 1.7-V adjustable I/O interface for low-voltage fast SRAMs.
IEEE J. Solid State Circuits, April, 1992

1990
A 23-ns 4-Mb CMOS SRAM with 0.2- mu A standby current.
IEEE J. Solid State Circuits, October, 1990

A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic.
IEEE J. Solid State Circuits, April, 1990

An alpha -immune, 2-V supply voltage SRAM using a polysilicon PMOS load cell.
IEEE J. Solid State Circuits, February, 1990

1989
A 9-ns 1-Mbit CMOS SRAM.
IEEE J. Solid State Circuits, October, 1989


  Loading...