Toshiaki Inoue

According to our database, Toshiaki Inoue authored at least 4 papers between 1994 and 1995.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1995

Cache-processor coupling: a fast and wide on-chip data cache design.

Masato Motomura, Toshiaki Inoue, Hachiro Yamada, Akihiko Konagaya

IEEE J. Solid State Circuits, April, 1995

Ordered multithreading: a novel technique for exploiting thread-level parallelism.

Masato Motomura, Toshiaki Inoue, Sunao Torii, Akihiko Konagaya

Proceedings of the IFIP WG10.3 working conference on Parallel architectures and compilation techniques, 1995

1994

A 500 MHz, 32 bit, 0.4 μm CMOS RISC processor.

Kazumasa Suzuki, Masakazu Yamashina, Takashi Nakayama, Masanori Izumikawa, Masahiro Nomura, Hiroyuki Igura, Hideki Heiuchi, Junichi Goto, Toshiaki Inoue, Youichi Koseki, Hitoshi Abiko, Kazuhiro Okabe, Atsuki Ono, Youich Yano, Hachiro Yamada

IEEE J. Solid State Circuits, December, 1994

A 300-MHz 16-b 0.5-μm BiCMOS digital signal processor core LSI.

Masahiro Nomura, Masakazu Yamashina, Junichi Goto, Toshiaki Inoue, Kazumasa Suzuki, Masato Motomura, Youichi Koseki, Benjamin S. Shih, Tadahiko Horiuchi, Nobuhisa Hamatake, Kouichi Kumagai, Tadayoshi Enomoto, Hachiro Yamada

IEEE J. Solid State Circuits, March, 1994