Toru Shimizu
Orcid: 0000-0003-1385-477X
According to our database1,
Toru Shimizu
authored at least 52 papers
between 1989 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2014, "For development of integrated multi-core microprocessors with large memories".
Timeline
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On csauthors.net:
Bibliography
2024
YJMob100K: City-Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories.
Dataset, March, 2024
2023
YJMob100K: City-Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories.
Dataset, November, 2023
Metropolitan Scale and Longitudinal Dataset of Anonymized Human Mobility Trajectories.
CoRR, 2023
2022
Proceedings of the 30th International Conference on Advances in Geographic Information Systems, 2022
2021
Improving Land Use Classification using Human Mobility-based Hierarchical Place Embeddings.
Proceedings of the 19th IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2021
2020
Learning Fine Grained Place Embeddings with Spatial Hierarchy from Human Mobility Trajectories.
CoRR, 2020
Unsupervised Translation via Hierarchical Anchoring: Functional Mapping of Places across Cities.
Proceedings of the KDD '20: The 26th ACM SIGKDD Conference on Knowledge Discovery and Data Mining, 2020
Proceedings of the SIGSPATIAL '20: 28th International Conference on Advances in Geographic Information Systems, 2020
Enabling Finer Grained Place Embeddings using Spatial Hierarchy from Human Mobility Trajectories.
Proceedings of the SIGSPATIAL '20: 28th International Conference on Advances in Geographic Information Systems, 2020
2019
Predicting Evacuation Decisions using Representations of Individuals' Pre-Disaster Web Search Behavior.
Proceedings of the 25th ACM SIGKDD International Conference on Knowledge Discovery & Data Mining, 2019
Proceedings of the 27th ACM SIGSPATIAL International Conference on Advances in Geographic Information Systems, 2019
Proceedings of the Information Retrieval Technology, 2019
2018
Optimization of Resonant Capacitance in Wireless Power Transfer System with 3-D Stacked Two Receivers.
IEICE Trans. Electron., 2018
Design Methodology in Wireless Power Transfer System for 3-D Stacked Multiple Receivers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 56th Annual Meeting of the Association for Computational Linguistics, 2018
2017
An Energy-Efficient Task Scheduling for Near-Realtime Systems with Execution Time Variation.
IEICE Trans. Inf. Syst., 2017
Proceedings of the 13th NTCIR Conference, 2017
Proceedings of the International SoC Design Conference, 2017
Proceedings of the International SoC Design Conference, 2017
2016
An adaptive energy-efficient task scheduling under execution time variation based on statistical analysis.
Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016
Proceedings of the International SoC Design Conference, 2016
Normally-off power management for sensor nodes of global navigation satellite system.
Proceedings of the International SoC Design Conference, 2016
2014
Inf. Media Technol., 2014
Proceedings of the IEEE Non-Volatile Memory Systems and Applications Symposium, 2014
Proceedings of the Eighth IEEE/ACM International Symposium on Networks-on-Chip, 2014
Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014
2013
0.5 V Start-Up 87% Efficiency 0.75 mm<sup>2</sup> On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration.
IEEE J. Solid State Circuits, 2013
On-Chip Single-Inductor Dual-Output DC-DC Boost Converter Having Off-Chip Power Transistor Drive and Micro-Computer Controlled MPPT Modes.
IEICE Trans. Electron., 2013
Large-scale network organization in the avian forebrain: a connectivity matrix and theoretical analysis.
Frontiers Comput. Neurosci., 2013
2012
A 0.5V start-up 87% efficiency 0.75mm<sup>2</sup> on-chip feed-forward single-inductor dual-output (SIDO) boost DC-DC converter for battery and solar cell operation sensor network micro-computer integration.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
2011
0.8V start-up 92% efficiency on-chip boost DC-DC converters for battery operation micro-computers.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2009
IEEE J. Solid State Circuits, 2009
2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture.
IEEE J. Solid State Circuits, 2007
Continuous Design Efforts for Ubiquitous Network Era under the Physical Limitation of Advanced CMOS.
IEICE Trans. Electron., 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2006
Design and Evaluation of a Massively Parallel Processor Based on Matrix Architecture.
IEICE Trans. Electron., 2006
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2006
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
J. Robotics Mechatronics, 2005
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005
2004
A 600-MHz single-chip multiprocessor with 4.8-GB/s internal shared pipelined bus and 512-kB internal memory.
IEEE J. Solid State Circuits, 2004
Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2004
2002
IEEE Trans. Consumer Electron., 2002
1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1997
1989
Proceedings of the Computer Design: VLSI in Computers and Processors, 1989