Toru Sano

According to our database, Toru Sano authored at least 17 papers between 2008 and 2020.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2020

A 20.5 TOPS Multicore SoC With DNN Accelerator and Image Signal Processor for Automotive Applications.

Yutaka Yamada, Masato Uchiyama, Masashi Jobashi, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Yoshinari Ojima, Ryusuke Murakami, Takashi Yoshikawa, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda

IEEE J. Solid State Circuits, 2020

2019

A 20.5TOPS and 217.3GOPS/mm² Multicore SoC with DNN Accelerator and Image Signal Processor Complying with ISO26262 for Automotive Applications.

Yutaka Yamada, Toru Sano, Yasuki Tanabe, Yutaro Ishigaki, Soichiro Hosoda, Fumihiko Hyuga, Akira Moriya, Ryuji Hada, Atsushi Masuda, Masato Uchiyama, Tomohiro Koizumi, Takanori Tamai, Nobuhiro Sato, Jun Tanabe, Katsuyuki Kimura, Ryusuke Murakami, Takashi Yoshikawa

Proceedings of the IEEE International Solid- State Circuits Conference, 2019

2015

On Estimation of Tangential Force in Railways Brake Systems by Fuzzy Inference.

Toru Sano, Yasunori Endo, Shin-ichi Nakazawa, Daisuke Hijikata

J. Adv. Comput. Intell. Intell. Informatics, 2015

18.2 A 1.9TOPS and 564GOPS/W heterogeneous multicore SoC with color-based object classification accelerator for image-recognition applications.

Jun Tanabe, Toru Sano, Yutaka Yamada, Tomoki Watanabe, Mayu Okumura, Manabu Nishiyama, Tadakazu Nomura, Kazushige Oma, Nobuhiro Sato, Moriyasu Banno, Hiroo Hayashi, Takashi Miyamori

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

Architecture and Evaluation of Low Power Many-Core SoC with Two 32-Core Clusters.

Takashi Miyamori, Hui Xu, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Jun Tanabe

IEICE Trans. Electron., 2014

An evaluation of an energy efficient many-core SoC with parallelized face detection.

Hiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Development of low power many-core SoC for multimedia applications.

Takashi Miyamori, Hui Xu, Takeshi Kodaka, Hiroyuki Usui, Toru Sano, Jun Tanabe

Proceedings of the Design, Automation and Test in Europe, 2013

A near-future prediction method for low power consumption on a many-core processor.

Takeshi Kodaka, Akira Takeda, Shunsuke Sasaki, Akira Yokosawa, Toshiki Kizu, Takahiro Tokuyoshi, Hui Xu, Toru Sano, Hiroyuki Usui, Jun Tanabe, Takashi Miyamori, Nobu Matsumoto

Proceedings of the Design, Automation and Test in Europe, 2013

2012

A low power many-core SoC with two 32-core clusters connected by tree based NoC for multimedia applications.

Hui Xu, Jun Tanabe, Hiroyuki Usui, Soichiro Hosoda, Toru Sano, Kazumasa Yamamoto, Takeshi Kodaka, Nobuhiro Nonogaki, Nau Ozaki, Takashi Miyamori

Proceedings of the Symposium on VLSI Circuits, 2012

2010

Reducing power consumption for Dynamically Reconfigurable Processor Array with Partially Fixed Configuration Mapping.

Kazuei Hironaka, Masayuki Kimura, Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Proceedings of the International Conference on Field-Programmable Technology, 2010

MuCCRA-3: a low power dynamically reconfigurable processor array.

Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Masayuki Kimura, Hideharu Amano

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009

Fine Grain Partial Reconfiguration for energy saving in Dynamically Reconfigurable Processors.

Toru Sano, Yoshiki Saito, Masaru Kato, Hideharu Amano

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

MuCCRA-Cube: A 3D dynamically reconfigurable processor with inductive-coupling link.

Shotaro Saito, Yoshinori Kohama, Yasufumi Sugimori, Yohei Hasegawa, Hiroki Matsutani, Toru Sano, Kazutaka Kasuga, Yoichi Yoshida, Kiichi Niitsu, Noriyuki Miura, Tadahiro Kuroda, Hideharu Amano

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Configuration with Self-Configured Datapath: A High Speed Configuration Method for Dynamically Reconfigurable Processors.

Toru Sano, Yoshiki Saito, Hideharu Amano

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

A Real Chip Evaluation of MuCCRA-3: A Low Power Dycamically Reconfigurable Processor Array.

Yoshiki Saito, Toru Sano, Masaru Kato, Vasutan Tunbunheng, Yoshihiro Yasuda, Hideharu Amano

Proceedings of the 2009 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2009

2008

Exploring the optimal size for multicasting configuration data of dynamically reconfigurable processors.

Takuro Nakamura, Toru Sano, Yohei Hasegawa, Satoshi Tsutsumi, Vasutan Tunbunheng, Hideharu Amano

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Instruction buffer mode for multi-context Dynamically Reconfigurable Processors.

Toru Sano, Masaru Kato, Satoshi Tsutsumi, Yohei Hasegawa, Hideharu Amano

Proceedings of the FPL 2008, 2008