Toru Koizumi

Orcid: 0000-0003-0990-1916

Affiliations:
  • University of Tokyo, Japan


According to our database1, Toru Koizumi authored at least 13 papers between 2018 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

2018
2019
2020
2021
2022
2023
2024
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1
2
3
4
5
1
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3
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2
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1
3

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Other 

Links

Online presence:

On csauthors.net:

Bibliography

2024
TURBULENCE: Complexity-Effective Out-of-Order Execution on GPU With Distance-Based ISA.
IEEE Comput. Archit. Lett., 2024

2023
A Principal Factor of Performance in Decoupled Front-End.
IEICE Trans. Inf. Syst., December, 2023

Clockhands: Rename-free Instruction Set Architecture for Out-of-order Processors.
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023

An Out-of-Order Superscalar Processor Using STRAIGHT Architecture in 28 nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

A Sound and Complete Algorithm for Code Generation in Distance-Based ISA.
Proceedings of the 32nd ACM SIGPLAN International Conference on Compiler Construction, 2023

2022
T-SKID: Predicting When to Prefetch Separately from Address Prediction.
Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

2021
Accurate and Fast Performance Modeling of Processors with Decoupled Front-end.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

Compiling and Optimizing Real-world Programs for STRAIGHT ISA.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021

2020
A High-Performance Out-of-Order Soft Processor Without Register Renaming.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

2019
An Open Source FPGA-Optimized Out-of-Order RISC-V Soft Processor.
Proceedings of the International Conference on Field-Programmable Technology, 2019

2018
STRAIGHT: Hazardless Processor Architecture Without Register Renaming.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Reduction of Instruction Increase Overhead by STRAIGHT Compiler.
Proceedings of the Sixth International Symposium on Computing and Networking, 2018

An Area-Efficient Out-of-Order Soft-Core Processor Without Register Renaming.
Proceedings of the International Conference on Field-Programmable Technology, 2018


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