Toru Iwata

According to our database, Toru Iwata authored at least 7 papers between 1996 and 2018.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2018

An ultra-wide range (0.01-240 Gbps) transmitter with latched AC-coupled driver and dummy data transient generator.

Tsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Yutaka Terada, Toru Iwata

IEICE Electron. Express, 2018

2014

A jitter suppression technique against data pattern dependency on high-speed interfaces for highly integrated SoCs.

Tsuyoshi Ebuchi, Taku Toshikawa, Seiji Watanabe, Tomohiro Tsuchiya, Yutaka Terada, Tomoko Chiba, Keijiro Umehara, Toru Iwata, Takefumi Yoshikawa

IEICE Electron. Express, 2014

2011

An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration.

Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa

IEEE J. Solid State Circuits, 2011

2008

An Over-1-Gb/s Transceiver Core for Integration Into Large System-on-Chips for Consumer Electronics.

Takefumi Yoshikawa, Takashi Hirata, Tsuyoshi Ebuchi, Toru Iwata, Yukio Arima, Hiroyuki Yamauchi

IEEE Trans. Very Large Scale Integr. Syst., 2008

2005

A Spread Spectrum Clock Generator Using Digital Tracking Scheme.

Takefumi Yoshikawa, Tsuyoshi Ebuchi, Yukio Arima, Toru Iwata

IEICE Trans. Electron., 2005

1997

A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture.

Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa

IEEE Trans. Very Large Scale Integr. Syst., 1997

1996

A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes.

Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996