Tooraj Nikoubin

According to our database, Tooraj Nikoubin authored at least 18 papers between 2009 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

TinyML for ECG Biometrics on Resource Constrained Devices.

Yogeswar Reddy Thota, Tooraj Nikoubin

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Area-power and Energy Efficient Substitution box (S-box) in Advanced Encryption Standard (AES).

Omid Bazgir, Satwik Gali, Tooraj Nikoubin

Proceedings of the Great Lakes Symposium on VLSI 2024, 2024

2019

Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures.

Hareesh-Reddy Basireddy, Karthikeya Challa, Tooraj Nikoubin

IEEE Trans. Very Large Scale Integr. Syst., 2019

Fast, Area & Energy Efficient Supergate Design With Multi-Output & Multi-Functional CDM Cells.

Tooraj Nikoubin, Hareesh-Reddy Basireddy

IEEE Access, 2019

Rounding Technique Analysis for Power-Area & Energy Efficient Approximate Multiplier Design.

Priyanka Lohray, Satwik Gali, Srirathan Rangisetti, Tooraj Nikoubin

Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

Fast & Energy Efficient Binary to BCD Converter with Complement Based Logic Design (CBLD) for BCD Multipliers.

Ashish Joshi, Srirathan Rangisetti, Priyanka Lohray, Tooraj Nikoubin

Proceedings of the IEEE 9th Annual Computing and Communication Workshop and Conference, 2019

2016

Energy and Area Efficient Three-Input XOR/XNORs With Systematic Cell Design Methodology.

Tooraj Nikoubin, Mahdieh Grailoo, Changzhi Li

IEEE Trans. Very Large Scale Integr. Syst., 2016

Complement Based Logic Design (CBLD) for Area and Power Efficiency of Arithmetic Building Blocks.

Nikhil Patil, Teja Geddamuri, Tooraj Nikoubin

Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

Wearable System for Obstacle Detection and Human Assistance Using Ultrasonic Sensor Array.

Ashish Patankar, Tooraj Nikoubin

Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

High Speed, Area and Power Efficient 32-bit Vedic Multipliers.

Mounika Mulkalapally, Jacob Manning, Paul Gatewood, Tooraj Nikoubin

Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

Power and Energy Efficient Standard Cell Library Design in CDM Logic Style with FinFET Transistors.

Ashish Joshi, Thejaswani Putta, Tooraj Nikoubin

Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

Power and Energy Efficient Standard Cells with CDM Logic Style for Optimization of Multiplier Structures.

Mahdieh Grailoo, Ashish Joshi, Mounika Mulkalapally, Tooraj Nikoubin

Proceedings of the 7th International Conference on Computing Communication and Networking Technologies, 2016

2015

Structural health monitoring of wind turbines using a low-cost portable k-band radar: An ab-initio field investigation.

Tooraj Nikoubin, José Maria Muñoz-Ferreras, Roberto Gómez-García, Daan Liang, Changzhi Li

Proceedings of the IEEE Topical Conference on Wireless Sensors and Sensor Networks, 2015

2014

Wireless radar devices for smart human-computer interaction.

Yiran Li, Changzhan Gu, Tooraj Nikoubin, Changzhi Li

Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

2013

Differential Cascode Voltage Switch (DCVS) Strategies by CNTFET Technology for Standard Ternary Logic.

Reza Faghih Mirzaee, Tooraj Nikoubin, Keivan Navi, Omid Hashemipour

Microelectron. J., 2013

2010

Simple Exact Algorithm for Transistor Sizing of Low-Power High-Speed Arithmetic Circuits.

Tooraj Nikoubin, Poona Bahrebar, Sara Pouri, Keivan Navi, Vaez Iravani

VLSI Design, 2010

Cell Design Methodology Based on Transmission Gate for Low-Power High-Speed Balanced XOR-XNOR Circuits in Hybrid-CMOS Logic Style.

Tooraj Nikoubin, Mahdieh Grailoo, Sayyed Hasan Mozafari

J. Low Power Electron., 2010

2009

A New Cell Design Methodology for Balanced XOR-XNOR Circuits for Hybrid-CMOS Logic.

Tooraj Nikoubin, Fatemeh Eslami, Amirali Baniasadi, Keivan Navi

J. Low Power Electron., 2009