Tony Nowatzki
Orcid: 0000-0001-8483-3824
According to our database1,
Tony Nowatzki
authored at least 51 papers
between 2012 and 2024.
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Bibliography
2024
PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation.
ACM Trans. Archit. Code Optim., December, 2024
Monza: An Energy-Minimal, General-Purpose Dataflow System-on-Chip for the Internet of Things.
IEEE Micro, 2024
2023
PIMSAB: A Processing-In-Memory System with Spatially-Aware Communication and Bit-Serial-Aware Computation.
CoRR, 2023
Proceedings of the 56th Annual IEEE/ACM International Symposium on Microarchitecture, 2023
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
Explainable-DSE: An Agile and Explainable Exploration of Efficient HW/SW Codesigns of Deep Learning Accelerators Using Bottleneck Analysis.
Proceedings of the 28th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2023
2022
IEEE Micro, 2022
IEEE Comput. Archit. Lett., 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022
Proceedings of the ISCA '22: The 49th Annual International Symposium on Computer Architecture, New York, New York, USA, June 18, 2022
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2022
Proceedings of the ASPLOS '22: 27th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, Lausanne, Switzerland, 28 February 2022, 2022
2021
Hardware Acceleration of Sparse and Irregular Tensor Computations of ML Models: A Survey and Insights.
Proc. IEEE, 2021
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021
Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2021
Mozart: Designing for Software Maturity and the Next Paradigm for Chip Architectures.
Proceedings of the IEEE Hot Chips 33 Symposium, 2021
Proceedings of the IEEE/ACM International Symposium on Code Generation and Optimization, 2021
2020
IEEE Micro, 2020
Proceedings of the 47th ACM/IEEE Annual International Symposium on Computer Architecture, 2020
Proceedings of the IEEE International Symposium on High Performance Computer Architecture, 2020
2019
IEEE Comput. Archit. Lett., 2019
μIR -An intermediate representation for transforming and optimizing the microarchitecture of application accelerators.
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture, 2019
Proceedings of the 46th International Symposium on Computer Architecture, 2019
2018
Hybrid optimization/heuristic instruction scheduling for programmable accelerator codesign.
Proceedings of the 27th International Conference on Parallel Architectures and Compilation Techniques, 2018
2017
Proceedings of the 44th Annual International Symposium on Computer Architecture, 2017
2016
Software transparent dynamic binary translation for coarse-grain reconfigurable architectures.
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 2016 IEEE International Symposium on High Performance Computer Architecture, 2016
Proceedings of the 2016 IEEE Hot Chips 28 Symposium (HCS), 2016
Proceedings of the Twenty-First International Conference on Architectural Support for Programming Languages and Operating Systems, 2016
2015
IEEE Micro, 2015
A Graph-Based Program Representation for Analyzing Hardware Specialization Approaches.
IEEE Comput. Archit. Lett., 2015
Performance evaluation of a DySER FPGA prototype system spanning the compiler, microarchitecture, and hardware implementation.
Proceedings of the 2015 IEEE International Symposium on Performance Analysis of Systems and Software, 2015
Proceedings of the 42nd Annual International Symposium on Computer Architecture, 2015
2014
A Scheduling Framework for Spatial Architectures Across Multiple Constraint-Solving Theories.
ACM Trans. Program. Lang. Syst., 2014
2013
Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers, ISBN: 978-3-031-01773-5, 2013
Proceedings of the ACM SIGPLAN Conference on Programming Language Design and Implementation, 2013
Breaking SIMD shackles with an exposed flexible microarchitecture and the access execute PDG.
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, 2013
2012
DySER: Unifying Functionality and Parallelism Specialization for Energy-Efficient Computing.
IEEE Micro, 2012
Design, integration and implementation of the DySER hardware accelerator into OpenSPARC.
Proceedings of the 18th IEEE International Symposium on High Performance Computer Architecture, 2012
Proceedings of the 2012 IEEE Hot Chips 24 Symposium (HCS), 2012