Toni Volkmer
According to our database1,
Toni Volkmer
authored at least 17 papers
between 2009 and 2022.
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Bibliography
2022
A sample efficient sparse FFT for arbitrary frequency candidate sets in high dimensions.
Numer. Algorithms, 2022
2021
Semi-supervised Learning for Aggregated Multilayer Graphs Using Diffuse Interface Methods and Fast Matrix-Vector Products.
SIAM J. Math. Data Sci., 2021
Sparse harmonic transforms II: best s-term approximation guarantees for bounded orthonormal product bases in sublinear-time.
Numerische Mathematik, 2021
A deterministic algorithm for constructing multiple rank-1 lattices of near-optimal size.
Adv. Comput. Math., 2021
2020
Sparse Fourier Transforms on Rank-1 Lattices for the Rapid and Low-Memory Approximation of Functions of Many Variables.
CoRR, 2020
Semi-supervised Learning for Multilayer Graphs Using Diffuse Interface Methods and Fast Matrix Vector Products.
CoRR, 2020
2019
Approximation of multivariate periodic functions based on sampling along multiple rank-1 lattices.
J. Approx. Theory, 2019
CoRR, 2019
2018
NFFT Meets Krylov Methods: Fast Matrix-Vector Products for the Graph Laplacian of Fully Connected Networks.
Frontiers Appl. Math. Stat., 2018
2017
Numerische Mathematik, 2017
2016
Frontiers Appl. Math. Stat., 2016
2015
Approximation of multivariate periodic functions by trigonometric polynomials based on rank-1 lattice sampling.
J. Complex., 2015
Approximation of multivariate periodic functions by trigonometric polynomials based on sampling along rank-1 lattice with generating vector of Korobov form.
J. Complex., 2015
2009
Design and Performance of a Grid of Asynchronously Clocked Run-Time Reconfigurable Modules on a FPGA.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009
Proceedings of the Parallel Computing: From Multicores and GPU's to Petascale, 2009
Impact of run-time reconfiguration on design and speed - A case study based on a grid of run-time reconfigurable modules inside a FPGA.
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009