High-performance, low-complexity decoding of generalized low-density parity-check codes. - Tong Zhang 002; Keshab K. Parhi (GLOBECOM, 2001)

A class of efficient-encoding generalized low-density parity-check codes. - Tong Zhang 002; Keshab K. Parhi (ICASSP, 2001)

On finite precision implementation of low density parity check codes decoder. - Tong Zhang 002; Zhongfeng Wang 001; Keshab K. Parhi (ISCAS (4), 2001)

Volume and Surface Area Distributions of Cracks in Concrete. - George Nagy; Tong Zhang 002; W. Randolph Franklin; Eric Landis; Edwin Nagy; Denis T. Keane (IWVF, 2001)

Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials. - Tong Zhang 002; Keshab K. Parhi (IEEE Trans. Computers, 2001)

On the high-speed VLSI implementation of errors-and-erasures correcting reed-solomon decoders. - Tong Zhang 002; Keshab K. Parhi (ACM Great Lakes Symposium on VLSI, 2002)

An FPGA Implementation of (3, 6)-Regular Low-Density Parity-Check Code Decoder. - Tong Zhang 002; Keshab K. Parhi (EURASIP J. Adv. Signal Process., 2003)

Surface Tortuosity and its Application to Analyzing Cracks in Concrete. - Tong Zhang 002; George Nagy (ICPR (2), 2004)

A high throughput limited search trellis decoder for convolutional code decoding. - Tong Zhang 002 (ISCAS (4), 2004)

Joint code-encoder-decoder design for LDPC coding system VLSI implementation. - Hao Zhong 006; Tong Zhang 002 (ISCAS (2), 2004)

Joint (3, k)-regular LDPC code and decoder/encoder design. - Tong Zhang 002; Keshab K. Parhi (IEEE Trans. Signal Process., 2004)

Parallelism/regularity-driven MIMO detection algorithm design. - Tong Zhang 002; Yan Xin 001; Sizhong Chen (ISCAS (5), 2005)

Parallel Logic Simulation of Million-Gate VLSI Circuits. - Lijuan Zhu; Gilbert Chen; Boleslaw K. Szymanski; Carl Tropper; Tong Zhang 002 (MASCOTS, 2005)

Self-timed dynamically pipelined adaptive signal processing system: a case study of DLMS equalizer for read channel. - Sizhong Chen; Tong Zhang 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Block-LDPC: a practical LDPC coding system design approach. - Hao Zhong 006; Tong Zhang 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2005)

Parallel high-throughput limited search trellis decoder VLSI design. - Fei Sun; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2005)

Nonlinear Soft-Output Signal Detector Design and Implementation for MIMO Communication Systems with High Spectral Efficiency. - Sizhong Chen; Fei Sun; Tong Zhang 002 (CICC, 2006)

VLSI Design of High-Rate Quasi-Cyclic LDPC Codes for Magnetic Recording Channel. - Hao Zhong 006; Tong Zhang 002; Erich F. Haratsch (CICC, 2006)

Relaxed tree search MIMO signal detection algorithm design and VLSI implementation. - Sizhong Chen; Tong Zhang 002; Manish Goel (ISCAS, 2006)

Multilevel flash memory on-chip error correction based on trellis coded modulation. - Fei Sun; Siddharth Devarajan; Kenneth Rose; Tong Zhang 002 (ISCAS, 2006)

Low power state-parallel relaxed adaptive Viterbi decoder design and implementation. - Fei Sun; Tong Zhang 002 (ISCAS, 2006)

High-rate quasi-cyclic LDPC codes for magnetic recording channel with low error floor. - Hao Zhong 006; Tong Zhang 002; Erich F. Haratsch (ISCAS, 2006)

Triple-rail MOS current mode logic for high-speed self-timed pipeline applications. - Kuan Zhou; Yifei Luo; Sizhong Chen; Allen Drake; John F. McDonald 001; Tong Zhang 002 (ISCAS, 2006)

Low Power Trellis Decoder with Overscaled Supply Voltage. - Yang Liu 016; Tong Zhang 002; Jiang Hu (SiPS, 2006)

Hybrid resistor/FET-logic demultiplexer architecture design for hybrid CMOS/nanodevice circuits. - Shu Li; Tong Zhang 002 (ICCD, 2007)

Low power soft-output signal detector design for wireless MIMO communication systems. - Sizhong Chen; Tong Zhang 002 (ISLPED, 2007)

On the selection of arithmetic unit structure in voltage overscaled soft digital signal processing. - Yang Liu 016; Tong Zhang 002 (ISLPED, 2007)

Soft Clock Skew Scheduling for Variation-Tolerant Signal Processing Circuits: A Case Study of Viterbi Decoders. - Yang Liu 016; Tong Zhang 002; Jiang Hu (ISQED, 2007)

Turbo- and LDPC-Coded MIMO-OFDM Systems: A Comparative Study. - Baoshen Tan; Yan Xin 001; Syed Aon Mujtaba; Tong Zhang 002 (PIMRC, 2007)

Design of on-chip error correction systems for multilevel NOR and NAND flash memories. - Fei Sun; Siddharth Devarajan; Kenneth Rose; Tong Zhang 002 (IET Circuits Devices Syst., 2007)

Low-Power State-Parallel Relaxed Adaptive Viterbi Decoder. - Fei Sun; Tong Zhang 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2007)

Relaxed K-Best MIMO Signal Detector Design and VLSI Implementation. - Sizhong Chen; Tong Zhang 002; Yan Xin 001 (IEEE Trans. Very Large Scale Integr. Syst., 2007)

Motion compensation aided motion adaptive de-interlacing for real-time video processing applications. - Hongbin Sun 001; Yang Liu; Nanning Zheng 001; Tong Zhang 002 (ACSCC, 2008)

Analysis of voltage overscaled computer arithmetics in low power signal processing systems. - Yang Liu 016; Tong Zhang 002; Keshab K. Parhi (ACSCC, 2008)

Realization of L2 Cache Defect Tolerance Using Multi-bit ECC. - Hongbin Sun 001; Nanning Zheng 001; Tong Zhang 002 (DFT, 2008)

Energy-efficient soft-output trellis decoder design using trellis quasi-reduction and importance-aware clock skew scheduling. - Yang Liu 016; Fei Sun; Tong Zhang 002 (ISCAS, 2008)

Spin-transfer torque magnetoresistive content addressable memory (CAM) cell structure design with enhanced search noise margin. - Wei Xu 021; Tong Zhang 002; Yiran Chen 001 (ISCAS, 2008)

Bypass Decoding: A Reduced-Complexity Decoding Technique for LDPC-Coded MIMO-OFDM Systems. - Yan Xin 001; Syed Aon Mujtaba; Tong Zhang 002; Jinhua Jiang (IEEE Trans. Veh. Technol., 2008)

Impact of parameter accuracy on 3D design. - Adam Beece; Kenneth Rose; Tong Zhang 002; Jiang-Qian Lu (3DIC, 2009)

Impacts of though-DRAM vias in 3D processor-DRAM integrated systems. - Qi Wu 006; Kenneth Rose; Jian-Qiang Lu; Tong Zhang 002 (3DIC, 2009)

Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration. - Zheng Xu 008; Adam Beece; Kenneth Rose; Tong Zhang 002; Jian-Qiang Lu (3DIC, 2009)

Improving VLIW Processor Performance Using Three-Dimensional (3D) DRAM Stacking. - Yangyang Pan; Tong Zhang 002 (ASAP, 2009)

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing. - Wei Xu 021; Yiran Chen 001; Xiaobin Wang; Tong Zhang 002 (DAC, 2009)

Improving multi-level NAND flash memory storage reliability using concatenated TCM-BCH coding. - Shu Li; Tong Zhang 002 (ACM Great Lakes Symposium on VLSI, 2009)

Efficient implementation of decoupling capacitors in 3D processor-dram integrated computing systems. - Qi Wu 006; Jian-Qiang Lu; Kenneth Rose; Tong Zhang 002 (ACM Great Lakes Symposium on VLSI, 2009)

Candidate bit based bit-flipping decoding algorithm for LDPC codes. - Guiqiang Dong; Yanan Li; Ningde Xie; Tong Zhang 002; Huaping Liu (ISIT, 2009)

Data manipulation techniques to reduce phase change memory write energy. - Wei Xu 021; Jibang Liu; Tong Zhang 002 (ISLPED, 2009)

Architecture design exploration of three-dimensional (3D) integrated DRAM. - Rakesh S. Anigundi; Hongbin Sun 001; Jian-Qiang Lu; Kenneth Rose; Tong Zhang 002 (ISQED, 2009)

Exploratory study on circuit and architecture design of very high density diode-switch phase change memories. - Shu Li; Tong Zhang 002 (ISQED, 2009)

Thermal-Assisted Spin Transfer Torque Memory (STT-RAM) Cell Design Exploration. - Hai Li 001; Haiwen Xi; Yiran Chen 001; John Stricklin; Xiaobin Wang; Tong Zhang 002 (ISVLSI, 2009)

Using carbon nanotube in digital memories. - Shu Li; Tong Zhang 002 (NANOARCH, 2009)

3D DRAM Design and Application to 3D Multicore Systems. - Hongbin Sun 001; Jibang Liu; Rakesh S. Anigundi; Nanning Zheng 001; Jian-Qiang Lu; Kenneth Rose; Tong Zhang 002 (IEEE Des. Test Comput., 2009)

3-D Data Storage, Power Delivery, and RF/Optical Transceiver - Case Studies of 3-D Integration From System Design Perspectives. - Tong Zhang 002; Rino Micheloni; Guoyan Zhang; Zhaoran Rena Huang; James Jian-Qiang Lu (Proc. IEEE, 2009)

Leveraging Access Locality for the Efficient Use of Multibit Error-Correcting Codes in L2 Cache. - Hongbin Sun 001; Nanning Zheng 001; Tong Zhang 002 (IEEE Trans. Computers, 2009)

Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. - Yang Liu 016; Tong Zhang 002; Jiang Hu (IEEE Trans. Very Large Scale Integr. Syst., 2009)

DSP Systems using Three-Dimensional (3D) Integration Technology. - Tong Zhang 002; Yangyang Pan; Yiran Li (Handbook of Signal Processing Systems, 2010)

A nondestructive self-reference scheme for Spin-Transfer Torque Random Access Memory (STT-RAM). - Yiran Chen 001; Hai Li 001; Xiaobin Wang; Wenzhong Zhu; Wei Xu 021; Tong Zhang 002 (DATE, 2010)

DRAM-based FPGA enabled by three-dimensional (3d) memory stacking (abstract only). - Yangyang Pan; Tong Zhang 002 (FPGA, 2010)

Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. - Yiran Chen 001; Hai Li 001; Xiaobin Wang; Wenzhong Zhu; Wei Xu 021; Tong Zhang 002 (ISLPED, 2010)

Design of low-power variation tolerant signal processing systems with adaptive finite word-length configuration. - Yang Liu 016; Jibang Liu; Tong Zhang 002 (ISQED, 2010)

Using time-aware memory sensing to address resistance drift issue in multi-level phase change memory. - Wei Xu 021; Tong Zhang 002 (ISQED, 2010)

DiffECC: Improving SSD Read Performance Using Differentiated Error Correction Coding Schemes. - Guanying Wu; Xubin He; Ningde Xie; Tong Zhang 002 (MASCOTS, 2010)

Exploiting three-dimensional (3D) memory stacking to improve image data access efficiency for motion estimation accelerators. - Yiran Li; Yang Liu 016; Tong Zhang 002 (Signal Process. Image Commun., 2010)

Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory. - Guiqiang Dong; Shu Li; Tong Zhang 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2010)

A 1.1-Gb/s 115-pJ/bit Configurable MIMO Detector Using 0.13- muhboxm CMOS Technology. - Liang Liu 002; Fan Ye 001; Xiaojing Ma 001; Tong Zhang 002; Junyan Ren (IEEE Trans. Circuits Syst. II Express Briefs, 2010)

Improving Multi-Level NAND Flash Memory Storage Reliability Using Concatenated BCH-TCM Coding. - Shu Li; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage. - Yang Liu 016; Tong Zhang 002; Keshab K. Parhi (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Design of Spin-Torque Transfer Magnetoresistive RAM and CAM/TCAM with High Sensing and Search Speed. - Wei Xu 021; Tong Zhang 002; Yiran Chen 001 (IEEE Trans. Very Large Scale Integr. Syst., 2010)

Exploiting Memory Device Wear-Out Dynamics to Improve NAND Flash Memory System Performance. - Yangyang Pan; Guiqiang Dong; Tong Zhang 002 (FAST, 2011)

Design techniques to improve the device write margin for MRAM-based cache memory. - Hongbin Sun 001; Chuanyin Liu; Nanning Zheng 001; Tai Min; Tong Zhang 002 (ACM Great Lakes Symposium on VLSI, 2011)

Exploiting Heat-Accelerated Flash Memory Wear-Out Recovery to Enable Self-Healing SSDs. - Qi Wu 006; Guiqiang Dong; Tong Zhang 002 (HotStorage, 2011)

Special session on "3D chips: Challenges and opportunities". - Tong Zhang 002 (ICSAMOS, 2011)

Architecting high-performance energy-efficient soft error resilient cache under 3D integration technology. - Hongbin Sun 001; Pengju Ren; Nanning Zheng 001; Tong Zhang 002; Tao Li 006 (Microprocess. Microsystems, 2011)

Using Lossless Data Compression in Data Storage Systems: Not for Saving Space. - Ningde Xie; Guiqiang Dong; Tong Zhang 002 (IEEE Trans. Computers, 2011)

On the Use of Soft-Decision Error-Correction Codes in nand Flash Memory. - Guiqiang Dong; Ningde Xie; Tong Zhang 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2011)

Design Techniques to Facilitate Processor Power Delivery in 3-D Processor-DRAM Integrated Systems. - Qi Wu 006; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). - Wei Xu 021; Hongbin Sun 001; Xiaobin Wang; Yiran Chen 001; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

A Time-Aware Fault Tolerance Scheme to Improve Reliability of Multilevel Phase-Change Memory in the Presence of Significant Resistance Drift. - Wei Xu 021; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2011)

Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applications. - Yangyang Pan; Guiqiang Dong; Qi Wu 006; Tong Zhang 002 (HPCA, 2012)

Reducing data transfer latency of NAND flash memory with soft-decision sensing. - Guiqiang Dong; Yuelin Zou; Tong Zhang 002 (ICC, 2012)

Mutual-Information Optimized Quantization for LDPC Decoding of Accurately Modeled Flash Data - Jiadong Wang; Guiqiang Dong; Tong Zhang 002; Richard D. Wesel (CoRR, 2012)

LDPC Decoding with Limited-Precision Soft Information in Flash Memories - Jiadong Wang; Guiqiang Dong; Thomas A. Courtade; Hari Shankar; Tong Zhang 002; Richard D. Wesel (CoRR, 2012)

Reducing latency overhead caused by using LDPC codes in NAND flash memory. - Wenzhe Zhao; Guiqiang Dong; Hongbin Sun 001; Nanning Zheng 001; Tong Zhang 002 (EURASIP J. Adv. Signal Process., 2012)

A 130 nm 1.2 V/3.3 V 16 Kb Spin-Transfer Torque Random Access Memory With Nondestructive Self-Reference Sensing Scheme. - Yiran Chen 001; Hai Li 001; Xiaobin Wang; Wenzhong Zhu; Wei Xu 021; Tong Zhang 002 (IEEE J. Solid State Circuits, 2012)

Reducing DRAM Image Data Access Energy Consumption in Video Processing. - Yiran Li; Tong Zhang 002 (IEEE Trans. Multim., 2012)

Joint Source-Channel Coding and Channelization for Embedded Video Processing With Flash Memory Storage. - Yiran Li; Guiqiang Dong; Tong Zhang 002 (IEEE Trans. Signal Process., 2012)

Estimating Information-Theoretical nand Flash Memory Storage Capacity and its Implication to Memory System Design Space Exploration. - Guiqiang Dong; Yangyang Pan; Ningde Xie; Chandra Varanasi; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

Using Magnetic RAM to Build Low-Power and Soft Error-Resilient L1 Cache. - Hongbin Sun 001; Chuanyin Liu; Wei Xu 021; Jizhong Zhao; Nanning Zheng 001; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2012)

VLSI design of fuzzy-decision bit-flipping QC-LDPC decoder. - Wenzhe Zhao; Minjie Lv; Hongbin Sun 001; Nanning Zheng 001; Tong Zhang 002 (ASICON, 2013)

LDPC-in-SSD: making advanced error correction codes work effectively in solid state drives. - Kai Zhao 005; Wenzhe Zhao; Hongbin Sun 001; Tong Zhang 002; Xiaodong Zhang 001; Nanning Zheng 001 (FAST, 2013)

Scheduling Algorithms for Handling Updates in Shingled Magnetic Recording. - Kalyana Sundaram Venkataraman; Tong Zhang 002; Wenzhe Zhao; Hongbin Sun 001; Nanning Zheng 001 (NAS, 2013)

Using Quasi-EZ-NAND Flash Memory to Build Large-Capacity Solid-State Drives in Computing Systems. - Yangyang Pan; Guiqiang Dong; Ningde Xie; Tong Zhang 002 (IEEE Trans. Computers, 2013)

Using Multilevel Phase Change Memory to Build Data Storage: A Time-Aware System Design Perspective. - Qi Wu 006; Fei Sun; Wei Xu 021; Tong Zhang 002 (IEEE Trans. Computers, 2013)

Enabling NAND Flash Memory Use Soft-Decision Error Correction Codes at Minimal Read Latency Overhead. - Guiqiang Dong; Ningde Xie; Tong Zhang 002 (IEEE Trans. Circuits Syst. I Regul. Pap., 2013)

Exploiting workload dynamics to improve SSD read latency via differentiated error correction codes. - Guanying Wu; Xubin He; Ningde Xie; Tong Zhang 002 (ACM Trans. Design Autom. Electr. Syst., 2013)

Error Rate-Based Wear-Leveling for nand Flash Memory at Highly Scaled Technology Nodes. - Yangyang Pan; Guiqiang Dong; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Exploring the Use of Emerging Nonvolatile Memory Technologies in Future FPGAs. - Yangyang Pan; Yiran Li; Hongbin Sun 001; Wei Xu 021; Nanning Zheng 001; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2013)

Using Planar Embedded DRAM in Memory Intensive Signal Processing Circuits: Case Studies on LDPC Decoding and Motion Estimation. - Kalyana Sundaram Venkataraman; Yiran Li; Qi Wu 006; Ningde Xie; Hongbin Sun 001; Nanning Zheng 001; Tong Zhang 002 (J. Signal Process. Syst., 2013)

DSP Systems Using Three-Dimensional Integration Technology. - Tong Zhang 002; Yangyang Pan; Yiran Li (Handbook of Signal Processing Systems, 2013)

Over-clocked SSD: Safely running beyond flash memory chip I/O clock specs. - Kai Zhao 005; Kalyana S. Venkataraman; Xuebin Zhang; Jiangpeng Li; Ning Zheng; Tong Zhang 002 (HPCA, 2014)

Proximate control stream assisted video transcoding for heterogeneous content delivery network. - Xuebin Zhang; Yuan Li; Jiangpeng Li; Kai Zhao 005; Tong Zhang 002 (ICIP, 2014)

Improving min-sum LDPC decoding throughput by exploiting intra-cell bit error characteristic in MLC NAND flash memory. - Wenzhe Zhao; Hongbin Sun 001; Minjie Lv; Guiqiang Dong; Nanning Zheng 001; Tong Zhang 002 (MSST, 2014)

Enhanced Precision Through Multiple Reads for LDPC Decoding in Flash Memories. - Jiadong Wang; Kasra Vakilinia; Tsung-Yi Chen; Thomas A. Courtade; Guiqiang Dong; Tong Zhang 002; Hari Shankar; Richard D. Wesel (IEEE J. Sel. Areas Commun., 2014)

OFWAR: Reducing SSD Response Time Using On-Demand Fast-Write-and-Rewrite. - Qi Wu 006; Tong Zhang 002 (IEEE Trans. Computers, 2014)

Realizing Unequal Error Correction for nand Flash Memory at Minimal Read Latency Overhead. - Jiangpeng Li; Kai Zhao 005; Jun Ma 012; Tong Zhang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Overclocking nand Flash Memory I/O Link in LDPC-Based SSDs. - Kai Zhao 005; Jiangpeng Li; Jun Ma 012; Rino Micheloni; Tong Zhang 002 (IEEE Trans. Circuits Syst. II Express Briefs, 2014)

Using Lifetime-Aware Progressive Programming to Improve SLC NAND Flash Memory Write Endurance. - Guiqiang Dong; Yangyang Pan; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2014)

Recent Advances in Design and Implementation of Signal Processing Systems. - Warren J. Gross; Naveen Verma; Tong Zhang 002 (J. Signal Process. Syst., 2014)

How Much Can Data Compressibility Help to Improve NAND Flash Memory Lifetime? - Jiangpeng Li; Kai Zhao 005; Xuebin Zhang; Jun Ma 012; Ming Zhao; Tong Zhang 002 (FAST, 2015)

Leveraging Progressive Programmability of SLC Flash Pages to Realize Zero-overhead Delta Compression for Metadata Storage. - Xuebin Zhang; Jiangpeng Li; Kai Zhao 005; Hao Wang 042; Tong Zhang 002 (HotStorage, 2015)

Exploring QoE for Power Efficiency: A Field Study on Mobile Videos with LCD Displays. - Zhisheng Yan; Qian Liu 001; Tong Zhang 002; Chang Wen Chen (ACM Multimedia, 2015)

On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory. - Wenzhe Zhao; Guiqiang Dong; Hui Han; Nanning Zheng 001; Tong Zhang 002 (Circuits Syst. Signal Process., 2015)

True-Damage-Aware Enumerative Coding for Improving nand Flash Memory Endurance. - Jiangpeng Li; Kai Zhao 005; Jun Ma 012; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Optimizing the Use of STT-RAM in SSDs Through Data-Dependent Error Tolerance. - Hao Wang 042; Kai Zhao 005; Jiangpeng Li; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2015)

Reducing Solid-State Storage Device Write Stress through Opportunistic In-place Delta Compression. - Xuebin Zhang; Jiangpeng Li; Hao Wang 042; Kai Zhao 005; Tong Zhang 002 (FAST, 2016)

Applying Software-based Memory Error Correction for In-Memory Key-Value Store: Case Studies on Memcached and RAMCloud. - Yin Li; Hao Wang 042; Xiaoqing Zhao; Hongbin Sun 001; Tong Zhang 002 (MEMSYS, 2016)

On the Use of DRAM with Unrepaired Weak Cells in Computing Systems. - Hao Wang 042; Yin Li; Xuebin Zhang; Xiaoqing Zhao; Hongbin Sun 001; Tong Zhang 002 (MEMSYS, 2016)

Guest Editorial Channel Modeling, Coding and Signal Processing for Novel Physical Memory Devices and Systems. - Shayan Garani Srinivasa; Tong Zhang 002; Ravi Hiranand Motwani; Haralampos Pozidis; Bane Vasic (IEEE J. Sel. Areas Commun., 2016)

Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device. - Hongbin Sun 001; Wenzhe Zhao; Minjie Lv; Guiqiang Dong; Nanning Zheng 001; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

An Information Theory Perspective for the Binary STT-MRAM Cell Operation Channel. - Jianxiao Yang; Benoit Geller; Meng Li 012; Tong Zhang 002 (IEEE Trans. Very Large Scale Integr. Syst., 2016)

Facilitating Magnetic Recording Technology Scaling for Data Center Hard Disk Drives through Filesystem-Level Transparent Local Erasure Coding. - Yin Li; Hao Wang 042; Xuebin Zhang; Ning Zheng; Shafa Dahandeh; Tong Zhang 002 (FAST, 2017)

Software Support Inside and Outside Solid-State Devices for High Performance and High Efficiency. - Feng Chen 005; Tong Zhang 002; Xiaodong Zhang 001 (Proc. IEEE, 2017)

Improving 3D DRAM Fault Tolerance Through Weak Cell Aware Error Correction. - Hao Wang 042; Kai Zhao 005; Minjie Lv; Xuebin Zhang; Hongbin Sun 001; Tong Zhang 002 (IEEE Trans. Computers, 2017)

Realizing Transparent OS/Apps Compression in Mobile Devices at Zero Latency Overhead. - Xuebin Zhang; Jiangpeng Li; Hao Wang 042; Danni Xiong; Jerry Qu; Hyunsuk Shin; Jung Pill Kim; Tong Zhang 002 (IEEE Trans. Computers, 2017)

Realizing Low-Cost Flash Memory Based Video Caching in Content Delivery Systems. - Xuebin Zhang; Danni Xiong; Kai Zhao 005; Chang Wen Chen; Tong Zhang 002 (IEEE Trans. Circuits Syst. Video Technol., 2018)

CrowdDBS: A Crowdsourced Brightness Scaling Optimization for Display Energy Reduction in Mobile Video. - Zhisheng Yan; Qian Liu 001; Tong Zhang 002; Chang Wen Chen (IEEE Trans. Mob. Comput., 2018)

Simultaneously reducing cost and improving performance of NVM-based block devices via transparent data compression. - Xubin Chen; Yin Li; Jingpeng Hao; Hyunsuk Shin; Michael Suh; Tong Zhang 002 (MEMSYS, 2019)

Mitigate HDD Fail-Slow by Pro-actively Utilizing System-level Data Redundancy with Enhanced HDD Controllability and Observability. - Jingpeng Hao; Yin Li; Xubin Chen; Tong Zhang 002 (MSST, 2019)

Reducing Flash Memory Write Traffic by Exploiting a Few MBs of Capacitor-Powered Write Buffer Inside Solid-State Drives (SSDs). - Xubin Chen; Yin Li; Tong Zhang 002 (IEEE Trans. Computers, 2019)

An Exploratory Study on Software-Defined Data Center Hard Disk Drives. - Yin Li; Xubin Chen; Ning Zheng; Jingpeng Hao; Tong Zhang 002 (ACM Trans. Storage, 2019)

POLARDB Meets Computational Storage: Efficiently Support Analytical Workloads in Cloud-Native Relational Database. - Wei Cao; Yang Liu 256; Zhushi Cheng; Ning Zheng; Wei Li; Wenjie Wu; Linqiang Ouyang; Peng Wang; Yijing Wang; Ray Kuan; Zhenjun Liu; Feng Zhu; et al. (FAST, 2020)

Re-think Data Management Software Design Upon the Arrival of Storage Hardware with Built-in Transparent Compression. - Ning Zheng; Xubin Chen; Jiangpeng Li; Qi Wu 006; Yang Liu 256; Yong Peng; Fei Sun; Hao Zhong 006; Tong Zhang 002 (HotStorage, 2020)

On the Design of SMR HDD Block Device Driver. - Jingpeng Hao; Xubin Chen; Yifan Qiao; Yuyang Zhang; Tong Zhang 002 (HPCC/DSS/SmartCity, 2020)

WAL-assisted Tiering: Painlessly Improving Your Favorite Log-Structured KV Store Instead of Building a New One. - Xubin Chen; Jingpeng Hao; Yifan Qiao; Tong Zhang 002 (MEMSYS, 2020)

Architecting Heterogeneous Memory Systems with DRAM Technology Only: A Case Study on Relational Database. - Yifan Qiao; Xubin Chen; Jingpeng Hao; Tong Zhang 002; Changsheng Xie; Fei Wu 005 (MCHPC@SC, 2020)

KallaxDB: A Table-less Hash-based Key-Value Store on Storage Hardware with Built-in Transparent Compression. - Xubin Chen; Ning Zheng; Shukun Xu; Yifan Qiao; Yang Liu 256; Jiangpeng Li; Tong Zhang 002 (DaMoN, 2021)

Implementing Flash-Cached Storage Systems Using Computational Storage Drive with Built-in Transparent Compression. - Jingpeng Hao; Xubin Chen; Yifan Qiao; Yuyang Zhang; Tong Zhang 002 (NAS, 2021)

Improving Relational Database Upon the Arrival of Storage Hardware with Built-in Transparent Compression. - Yifan Qiao; Xubin Chen; Jingpeng Hao; Jiangpeng Li; Qi Wu 006; Jingqiang Wang; Yang Liu 256; Tong Zhang 002 (NAS, 2021)

Closing the B+-tree vs. LSM-tree Write Amplification Gap on Modern Storage Hardware with Built-in Transparent Compression. - Yifan Qiao; Xubin Chen; Ning Zheng; Jiangpeng Li; Yang Liu 256; Tong Zhang 002 (FAST, 2022)

Elastic RAID: When RAID Meets SSDs with Built-in Transparent Compression. - Zheng Gu; Jiangpeng Li; Yong Peng; Yang Liu 256; Tong Zhang 002 (CoRR, 2022)

Elastic RAID: Implementing RAID over SSDs with Built-in Transparent Compression. - Zheng Gu; Jiangpeng Li; Yong Peng; Yang Liu 256; Tong Zhang 002 (SYSTOR, 2023)

Eliminating Storage Management Overhead of Deduplication over SSD Arrays Through a Hardware/Software Co-Design. - Yuhong Wen; Xiaogang Zhao; You Zhou 009; Tong Zhang 002; Shangjun Yang; Changsheng Xie; Fei Wu 005 (ASPLOS (2), 2024)