Tomoyuki Nakabayashi

According to our database, Tomoyuki Nakabayashi authored at least 10 papers between 2011 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2014

Detail Design and Evaluation of Fab Cache.

Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo

Proceedings of the Second International Symposium on Computing and Networking, 2014

Co-simulation framework for streamlining microprocessor development on standard ASIC design flow.

Tomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Energy Optimization using Fine-Grain Variable Stages Pipeline Processor Chip.

Tomoyuki Nakabayashi, Takahiro Sasaki, Hitoshi Nakamura, Kazuhiko Ohno, Toshio Kondo

Int. J. Netw. Comput., 2013

Design and evaluation of fine-grain-mode transition method based on dynamic memory access analysing for variable stages pipeline processor.

Takahiro Sasaki, Tomoyuki Nakabayashi, Kazumasa Nomura, Kazuhiko Ohno, Toshio Kondo

IET Comput. Digit. Tech., 2013

FabCache: Cache Design Automation for Heterogeneous Multi-core Processors.

Takaki Okamoto, Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo

Proceedings of the First International Symposium on Computing and Networking, 2013

Dynamic BTB Resizing for Variable Stages Superscalar Architecture.

Tomoyuki Nakabayashi, Takahiro Sasaki, Toshio Kondo

Proceedings of the First International Symposium on Computing and Networking, 2013

2012

Design and evaluation of variable stages pipeline processor with low-energy techniques.

Tomoyuki Nakabayashi, Takahiro Sasaki, I. K. Ohno, Toshio Kondo

IET Comput. Digit. Tech., 2012

Measurement of Low-Energy Processor Chip Using Fine-Grain Variable Stages Pipeline Architecture.

Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo

Proceedings of the Third International Conference on Networking and Computing, 2012

2011

Low power semi-static TSPC D-FFs using split-output latch.

Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo

Proceedings of the International SoC Design Conference, 2011

Design and evaluation of variable stages pipeline processor chip.

Tomoyuki Nakabayashi, Takahiro Sasaki, Kazuhiko Ohno, Toshio Kondo

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011