Tomoya Suzuki
Orcid: 0009-0008-3031-2693
According to our database1,
Tomoya Suzuki
authored at least 30 papers
between 2003 and 2024.
Collaborative distances:
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Bibliography
2024
Tool Path Design of Metal Powder Extrusion in Additive Manufacturing for Suppressing Shape Error Caused During Sintering.
Int. J. Autom. Technol., July, 2024
2023
CoRR, 2023
Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023
Proceedings of the Proceedings 26th International Conference on Extending Database Technology, 2023
2022
Design and Implementation of System for URL Signature Construction and Impact Assessment.
Proceedings of the 12th International Congress on Advanced Applied Informatics, 2022
2021
Approaching DRAM performance by using microsecond-latency flash memory for small-sized random read accesses: a new access method and its graph applications.
Proc. VLDB Endow., 2021
Proceedings of the 19th IEEE International Conference on Pervasive Computing and Communications Workshops and other Affiliated Events, 2021
Proceedings of the 55th Annual Conference on Information Sciences and Systems, 2021
2020
IEICE Trans. Electron., 2020
2019
Live Demonstration: FPGA-Based CNN Accelerator with Filter-Wise-Optimized Bit Precision.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 13th International Conference on Ubiquitous Information Management and Communication, 2019
2018
An 802.11ax 4 × 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer.
IEEE J. Solid State Circuits, 2018
An 802.11ax 4×4 spectrum-efficient WLAN AP transceiver SoC supporting 1024QAM with frequency-dependent IQ calibration and integrated interference analyzer.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A Neuromorphic Chip Optimized for Deep Learning and CMOS Technology With Time-Domain Analog and Digital Mixed-Signal Processing.
IEEE J. Solid State Circuits, 2017
2016
Time-domain neural network: A 48.5 TSOp/s/W neuromorphic chip optimized for deep learning and CMOS technology.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
Int. J. Pervasive Comput. Commun., 2015
2014
Proceedings of the 16th International Conference on Information Integration and Web-based Applications & Services, 2014
Proceedings of the Social Computing and Social Media, 2014
2013
Proceedings of the RoboCup 2013: Robot World Cup XVII [papers from the 17th Annual RoboCup International Symposium, 2013
2012
Proceedings of the FUZZ-IEEE 2012, 2012
2011
IEEE Micro, 2011
Proceedings of the 2011 IEEE International Conference on Robotics and Biomimetics, 2011
A multimodal wireless baseband core using a coarse-grained dynamic reconfigurable processor.
Proceedings of the 2011 IEEE Symposium on Low-Power and High-Speed Chips, 2011
2008
Proceedings of the 2008 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2008
2007
IEICE Trans. Inf. Syst., 2007
2006
Proceedings of the Intelligent Data Engineering and Automated Learning, 2006
Proceedings of the Computing and Combinatorics, 12th Annual International Conference, 2006
2005
Proceedings of the Entertainment Computing, 2005
2003
Proceedings of the Genetic and Evolutionary Computation, 2003