Tomoya Kitai
According to our database1,
Tomoya Kitai
authored at least 4 papers
between 2001 and 2005.
Collaborative distances:
Collaborative distances:
Timeline
2001
2002
2003
2004
2005
0
1
2
3
1
2
1
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2005
Failure Trace Analysis of Timed Circuits for Automatic Timing Constraints Derivation.
IEICE Trans. Inf. Syst., 2005
2002
Level Oriented Formal Model for Asynchronous Circuit Verification and its Efficient Analysis Method.
Proceedings of the 9th Pacific Rim International Symposium on Dependable Computing (PRDC 2002), 2002
Proceedings of the Computer Aided Verification, 14th International Conference, 2002
2001
Proceedings of the 8th Pacific Rim International Symposium on Dependable Computing (PRDC 2001), 2001