Tomoya Ishii

Orcid: 0000-0002-2789-5559

According to our database1, Tomoya Ishii authored at least 4 papers between 2015 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

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Bibliography

2023
Collision Prediction with Oncoming Pedestrians on Braille Blocks.
Proceedings of the 15th Asia-Pacific Workshop on Mixed and Augmented Reality co-located with TAICHI 2023, 2023

2016
Adaptive Comparator Bias-Current Control of 0.6 V Input Boost Converter for ReRAM Program Voltages in Low Power Embedded Applications.
IEEE J. Solid State Circuits, 2016

Heterogeneously integrated program voltage generator for 1.0V operation NAND flash with best mix & match of standard CMOS process and NAND flash process.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016

2015
0.6 V operation, 26% smaller voltage ripple, 9% energy efficient boost converter with adaptively optimized comparator bias-current for ReRAM program in low power IoT embedded applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015


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