Tomotaka Tanaka
Orcid: 0009-0009-0000-227X
According to our database1,
Tomotaka Tanaka
authored at least 7 papers
between 2009 and 2024.
Collaborative distances:
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Bibliography
2024
A 3-nm FinFET 27.6-Mbit/mm<sup>2</sup> Single-Port 6T SRAM Enabling 0.48-1.2 V Wide Operating Range With Far-End Pre-Charge and Weak-Bit Tracking.
IEEE J. Solid State Circuits, April, 2024
A 3nm Fin-FET 19.87-Mbit/mm<sup>2</sup> 2RW Pseudo Dual-Port 6T SRAM with High-R Wire Tracking and Sequential Access Aware Dynamic Power Reduction.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
2022
Neuroinformatics, 2022
2019
Proceedings of the 2019 International SoC Design Conference, 2019
2018
Proceedings of the International SoC Design Conference, 2018
2009
The relationship between leukoaraiosis volume and parameters of carotid artery duplex ultrasonographic scanning in asymptomatic diabetic patients.
Comput. Medical Imaging Graph., 2009