Tomokazu Ishihara

According to our database, Tomokazu Ishihara authored at least 6 papers between 2006 and 2008.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2008

A Sub 100 mW H.264 MP@L4.1 Integer-Pel Motion Estimation Processor Core for MBAFF Encoding with Reconfigurable Ring-Connected Systolic Array and Segmentation-Free, Rectangle-Access Search-Window Buffer.

Yuichiro Murachi, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2008

A sub 100 mW H.264/AVC MP@L4.1 integer-pel motion estimation processor VLSI for MBAFF encoding.

Yuichiro Murachi, Kosuke Mizuno, Junichi Miyakoshi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Tetsuya Kamino, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

An H.264/AVC MP@L4.1 quarter-pel motion estimation processor VLSI for real-time MBAFF encoding.

Kosuke Mizuno, Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Fang Yin, Jangchung Lee, Hiroshi Kawaguchi, Masahiko Yoshimoto

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2006

A Sub-mW H.264 Baseline-Profile Motion Estimation Processor Core with a VLSI-Oriented Block Partitioning Strategy and SIMD/Systolic-Array Architecture.

Junichi Miyakoshi, Yuichiro Murachi, Tetsuro Matsuno, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masayuki Miyama, Masahiko Yoshimoto

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006

A Power- and Area-Efficient SRAM Core Architecture with Segmentation-Free and Horizontal/Vertical Accessibility for Super-Parallel Video Processing.

Junichi Miyakoshi, Yuichiro Murachi, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto

IEICE Trans. Electron., 2006

A Power- and Area-Efficient SRAM Core Architecture for Super-Parallel Video Processing.

Junichi Miyakoshi, Yuichiro Murachi, Masaki Hamamoto, Takahiro Iinuma, Tomokazu Ishihara, Hiroshi Kawaguchi, Masahiko Yoshimoto, Tetsuro Matsuno

Proceedings of the IFIP VLSI-SoC 2006, 2006