Tomoichi Hayashi

According to our database, Tomoichi Hayashi authored at least 4 papers between 2005 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

A two-stage-pipeline CPU of SH-2 architecture implemented on FPGA and SoC for IoT, edge AI and robotic applications.

Kesami Hagiwara, Tomoichi Hayashi, Shumpei Kawasaki, Fumio Arakawa, Oleg Endo, Hayato Nomura, Akira Tsukamoto, Duong Nguyen, Binh Nguyen, Anh Tran, Hoan Hyunh, Ikuo Kudoh, Cong-Kha Pham

Proceedings of the 2018 IEEE Symposium in Low-Power and High-Speed Chips, 2018

2009

An embedded processor core for consumer appliances with 5.6 GFLOPS and 73M polygons/s FPU.

Fumio Arakawa, Takashi Okada, Tomoichi Hayashi, Osamu Nishii, Toshihiro Hattori

Microprocess. Microsystems, 2009

2008

An 8640 MIPS SoC with Independent Power-Off Control of 8 CPUs and 8 RAMs by An Automatic Parallelizing Compiler.

Masayuki Ito, Toshihiro Hattori, Yutaka Yoshida, Kiyoshi Hayase, Tomoichi Hayashi, Osamu Nishii, Yoshihiko Yasu, Atsushi Hasegawa, Masashi Takada, Hiroyuki Mizuno, Kunio Uchiyama, Toshihiko Odaka, Jun Shirako, Masayoshi Mase, Keiji Kimura, Hironori Kasahara

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2005

An Exact Leading Non-Zero Detector for a Floating-Point Unit.

Fumio Arakawa, Tomoichi Hayashi, Masakazu Nishibori

IEICE Trans. Electron., 2005