Tomohisa Wada
According to our database1,
Tomohisa Wada
authored at least 14 papers
between 1998 and 2019.
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Bibliography
2019
A Denoising Autoencoder based wireless channel transfer function estimator for OFDM communication system.
Proceedings of the International Conference on Artificial Intelligence in Information and Communication, 2019
Comparative study of supervised learning algorithms for student performance prediction.
Proceedings of the International Conference on Artificial Intelligence in Information and Communication, 2019
2016
Proceedings of the International Symposium on Intelligent Signal Processing and Communication Systems, 2016
2010
J. Comput. Networks Commun., 2010
Pilot-Aided Channel Estimation for WiMAX 802.16e Downlink Partial Usage of Subchannel System Using Least Squares Line Fitting.
IEICE Trans. Commun., 2010
Proceedings of the Advances in Computer Science and Information Technology, 2010
Modified Structures of Viterbi Alogrithm for Forced-State Method in Concatenated Coding System of ISDB-T.
Proceedings of the Advances in Computer Science and Information Technology, 2010
ISI and ICI Suppression for Mobile OFDM System by Using a Hybrid 2-Layer Diversity Receiver.
Proceedings of the Mobile Wireless Middleware, Operating Systems, and Applications - Third International Conference, Mobilware 2010, Chicago, IL, USA, June 30, 2010
2009
The Implementation of a 2/4/8 Antennas Configurable Diversity OFDM Receiver for Mobile HDTV Application.
Int. J. Digit. Multim. Broadcast., 2009
Performance Analysis of a Joint Space-Time Block Codes and Channel Estimation Scheme in DL-PUSC Mode of Mobile WiMAX.
Proceedings of the Communications Infrastructure. Systems and Applications in Europe, 2009
2008
Implementation of Joint Pre-FFT Adaptive Array Antenna and Post-FFT Space Diversity Combining for Mobile ISDB-T Receiver.
IEICE Trans. Commun., 2008
2006
Joint Hardware-Software Implementation of Adaptive Array Antenna for ISDB-T Reception.
IEICE Trans. Commun., 2006
1999
IEEE J. Solid State Circuits, 1999
1998
A 5-MHz, 3.6-mW, 1.4-V SRAM with nonboosted, vertical bipolar bit-line contact memory cell.
IEEE J. Solid State Circuits, 1998