Tomohiro Ueno

According to our database, Tomohiro Ueno authored at least 43 papers between 2013 and 2025.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2025

Multifacets of lossy compression for scientific data in the Joint-Laboratory of Extreme Scale Computing.

Franck Cappello, Mario C. Acosta, Emmanuel Agullo, Hartwig Anzt, Jon Calhoun, Sheng Di, Luc Giraud, Thomas Grützmacher, Sian Jin, Kentaro Sano, Kento Sato, Amarjit Singh, Dingwen Tao, Jiannan Tian, Tomohiro Ueno, Robert Underwood, Frédéric Vivien, Xavier Yepes, Kazutomo Yoshii, Boyuan Zhang

Future Gener. Comput. Syst., 2025

2024

Automated parallel execution of distributed task graphs with FPGA clusters.

Juan Miguel De Haro Ruiz, Carlos Álvarez-Martínez, Daniel Jiménez-González, Xavier Martorell, Tomohiro Ueno, Kentaro Sano, Burkhard Ringlein, François Abel, Beat Weiss

Future Gener. Comput. Syst., 2024

A Productive HLS Simulation Approach for Multi-FPGA Systems.

Haruto Ikehara, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

HLS Implementation of a Building Cube Stencil Computation Framework for an FPGA Accelerator.

Daiki Furukawa, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano

Proceedings of the IEEE International Conference on Consumer Electronics, 2024

Flexible Systolic Array Platform on Virtual 2-D Multi-FPGA Plane.

Tomohiro Ueno, Emanuele Del Sozzo, Kentaro Sano

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2024

2023

VCSN: Virtual Circuit-Switching Network for Flexible and Simple-to-Operate Communication in HPC FPGA Cluster.

Tomohiro Ueno, Kentaro Sano

ACM Trans. Reconfigurable Technol. Syst., June, 2023

Streaming Hardware Compressor Generator Framework.

Kazutomo Yoshii, Tomohiro Ueno, Kentaro Sano, Antonino Miceli, Franck Cappello

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Hardware Specialization: Estimating Monte Carlo Cross-Section Lookup Kernel Performance and Area.

Kazutomo Yoshii, John R. Tramm, Bryce Allen, Tomohiro Ueno, Kentaro Sano, Andrew R. Siegel, Pete Beckman

Proceedings of the SC '23 Workshops of The International Conference on High Performance Computing, 2023

Less for More: Reducing Intra-CGRA Connectivity for Higher Performance and Efficiency in HPC.

Boma A. Adhi, Carlos Cortes, Emanuele Del Sozzo, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2023

ESSPER: Elastic and Scalable FPGA-Cluster System for High-Performance Reconfigurable Computing with Supercomputer Fugaku.

Kentaro Sano, Atsushi Koshiba, Takaaki Miyajima, Tomohiro Ueno

Proceedings of the International Conference on High Performance Computing in Asia-Pacific Region, 2023

2022

FPGA-Dedicated Network vs. Server Network for Pipelined Computing with Multiple FPGAs.

Tomohiro Ueno, Takaaki Miyajima, Kentaro Sano

Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

Stream Computation of 3D Approximate Convex Hulls with an FPGA.

Tatsuma Mori, Daiki Furukawa, Keigo Motoyoshi, Haruto Ikehara, Kaito Ohira, Taito Manabe, Yuichiro Shibata, Tomohiro Ueno, Kentaro Sano

Proceedings of the HEART 2022: International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, Tsukuba, Japan, June 9, 2022

ESSPER: Elastic and Scalable System for High-Performance Reconfigurable Computing with Software-bridged APIs.

Kentaro Sano, Atsushi Koshiba, Takaaki Miyajima, Tomohiro Ueno

Proceedings of the International Conference on Field-Programmable Technology, 2022

Exploring Inter-tile Connectivity for HPC-oriented CGRA with Lower Resource Usage.

Boma A. Adhi, Carlos Cortes, Tomohiro Ueno, Yiyu Tan, Takuya Kojima, Artur Podobas, Kentaro Sano

Proceedings of the International Conference on Field-Programmable Technology, 2022

2021

Virtual Circuit-Switching Network with Flexible Topology for High-Performance FPGA Cluster.

Tomohiro Ueno, Atsushi Koshiba, Kentaro Sano

Proceedings of the 32nd IEEE International Conference on Application-specific Systems, 2021

2020

Performance Evaluation of Pipelined Communication Combined with Computation in OpenCL Programming on FPGA.

Norihisa Fujita, Ryohei Kobayashi, Yoshiki Yamaguchi, Tomohiro Ueno, Kentaro Sano, Taisuke Boku

Proceedings of the 2020 IEEE International Parallel and Distributed Processing Symposium Workshops, 2020

Comparison of Direct and Indirect Networks for High-Performance FPGA Clusters.

Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa

Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2020

2019

Scalability Analysis of Deeply Pipelined Tsunami Simulation with Multiple FPGAs.

Antoniette Mondigo, Tomohiro Ueno, Kentaro Sano, Hiroyuki Takizawa

IEICE Trans. Inf. Syst., 2019

Hybrid Network Utilization for Efficient Communication in a Tightly Coupled FPGA Cluster.

Tomohiro Ueno, Takaaki Miyajima, Antoniette Mondigo, Kentaro Sano

Proceedings of the International Conference on Field-Programmable Technology, 2019

2018

High-productivity Programming and Optimization Framework for Stream Processing on FPGA.

Jinpil Lee, Tomohiro Ueno, Mitsuhisa Sato, Kentaro Sano

Proceedings of the 9th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2018

Performance Analysis of Hardware-Based Numerical Data Compression on Various Data Formats.

Tomohiro Ueno, Kentaro Sano, Takashi Furusawa

Proceedings of the 2018 Data Compression Conference, 2018

2017

Bandwidth Compression of Floating-Point Numerical Data Streams for FPGA-Based High-Performance Computing.

Tomohiro Ueno, Kentaro Sano, Satoru Yamamoto

ACM Trans. Reconfigurable Technol. Syst., 2017

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay.

Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEEE J. Solid State Circuits, 2017

Design and scalability analysis of bandwidth-compressed stream computing with multiple FPGAs.

Antoniette Mondigo, Tomohiro Ueno, Daichi Tanaka, Kentaro Sano, Satoru Yamamoto

Proceedings of the 12th International Symposium on Reconfigurable Communication-centric Systems-on-Chip, 2017

FPGA-based Stream Computing for High-Performance N-Body Simulation using Floating-Point DSP Blocks.

Kentaro Sano, Shin Abiko, Tomohiro Ueno

Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2017

Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network.

Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Proceedings of the 12th IEEE International Conference on ASIC, 2017

2016

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture.

Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

IEEE J. Solid State Circuits, 2016

A 0.0055mm² 480µW Fully Synthesizable PLL Using Stochastic TDC in 28nm FDSOI.

Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa

IEICE Trans. Electron., 2016

13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay.

Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation.

Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique.

Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

IEEE J. Solid State Circuits, 2015

19.5 An HCI-healing 60GHz CMOS transceiver.

Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture.

Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

An HDL-synthesized gated-edge-injection PLL with a current output DAC.

Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection.

Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Stream Processor Generator for HPC to Embedded Applications on FPGA-based System Platform.

Kentaro Sano, Hayato Suzuki, Ryo Ito, Tomohiro Ueno, Satoru Yamamoto

CoRR, 2014

20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding.

Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

15.1 A 0.0066mm² 780μW fully synthesizable PLL with a current-output DAC and an interpolative phase-coupled oscillator using edge-injection technique.

Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

Effects of densely sampled dipole field on quantitative susceptibility mapping.

Yuya Umemoto, Mai Murashima, Tomohiro Ueno, Naozo Sugimoto

Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Bandwidth compression of multiple numerical data streams for high performance custom computing.

Tomohiro Ueno, Ryo Ito, Kentaro Sano, Satoru Yamamoto

Proceedings of the IEEE 25th International Conference on Application-Specific Systems, 2014

2013

Efficient custom computing of fully-streamed lattice boltzmann method on tightly-coupled FPGA cluster.

Kentaro Sano, Yoshiaki Kono, Hayato Suzuki, Ryotaro Chiba, Ryo Ito, Tomohiro Ueno, Kyo Koizumi, Satoru Yamamoto

SIGARCH Comput. Archit. News, 2013

Effective digitized spatial size of unit dipole field in Quantitative Susceptibility Mapping.

Mai Murashima, Tomohiro Ueno, Naozo Sugimoto

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Parameterized Design and Evaluation of Bandwidth Compressor for Floating-Point Data Streams in FPGA-Based Custom Computing.

Tomohiro Ueno, Yoshiaki Kono, Kentaro Sano, Satoru Yamamoto

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013