Tomohiro Korikawa

Orcid: 0000-0003-4060-0396

According to our database1, Tomohiro Korikawa authored at least 17 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Device Type Classification Based on Two-Stage Traffic Behavior Analysis.
IEICE Trans. Commun., January, 2024

An Adaptive Rule-based Path Selection Method using Link Information in Non-Terrestrial Networks.
Proceedings of the 10th IEEE International Conference on Network Softwarization, 2024

A Routing Method with Link Information-based Rule Selection in Non-Terrestrial Networks.
Proceedings of the International Conference on Computing, Networking and Communications, 2024

Trend Encoder with Attentive Neural Process: Node Performance Extrapolation for Non-Time-Series Datasets.
Proceedings of the International Conference on Computing, Networking and Communications, 2024

Meta Learner-Based Transfer Learning: Bridging Simulation and Actual Router Metrics.
Proceedings of the 25th IEEE International Conference on High Performance Switching and Routing, 2024

2023
Recursive Router Metrics Prediction Using Machine Learning-Based Node Modeling for Network Digital Replica.
IEEE Access, 2023

Traffic Behavior-based Device Type Classification.
Proceedings of the International Conference on Computing, Networking and Communications, 2023

Time-Topology Routing in 3D Networks.
Proceedings of the International Conference on Computing, Networking and Communications, 2023

2022
Memory Network Architecture for Packet Processing in Functions Virtualization.
IEEE Trans. Netw. Serv. Manag., 2022

Network Digital Replica using Neural-Network-based Network Node Modeling.
Proceedings of the 8th IEEE International Conference on Network Softwarization, 2022

Recursive Router Metrics Prediction Using ML-based Node Modeling for Network Digital Replica.
Proceedings of the IEEE Global Communications Conference, 2022

2021
Packet Processing Architecture with Off-Chip Last Level Cache Using Interleaved 3D-Stacked DRAM.
IEICE Trans. Commun., 2021

2020
Packet Processing Architecture Using Last-Level-Cache Slices and Interleaved 3D-Stacked DRAM.
IEEE Access, 2020

2019
Carrier-Scale Packet Processing Architecture Using Interleaved 3D-Stacked DRAM and Its Analysis.
IEEE Access, 2019

Packet Processing Architecture With Off-Chip LLC Using Interleaved 3D-Stacked DRAM.
Proceedings of the 20th IEEE International Conference on High Performance Switching and Routing, 2019

2018
Carrier-Scale Packet Processing System Using Interleaved 3D-Stacked DRAM.
Proceedings of the 2018 IEEE International Conference on Communications, 2018

2017
Toward carrier-scale general-purpose node.
Proceedings of the 2017 International Conference on Computing, 2017


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