Tomoharu Tanaka

According to our database, Tomoharu Tanaka authored at least 14 papers between 1989 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2016

7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory.

Tomoharu Tanaka, Mark Helm, Tommaso Vali, Ramin Ghodsi, Koichi Kawai, Jae-Kwan Park, Shigekazu Yamada, Feng Pan, Yuichi Einaga, Ali Ghalam, Toru Tanzawa, Jason Guo, Takaaki Ichikawa, Erwin Yu, Satoru Tamada, Tetsuji Manabe, Jiro Kishimoto, Yoko Oikawa, Yasuhiro Takashima, Hidehiko Kuge, Midori Morooka, Ali Mohammadzadeh, Jong Kang, Jeff Tsai, Emanuele Sirizotti, Eric Lee, Luyen Vu, Yuxing Liu, Hoon Choi, Kwonsu Cheon, Daesik Song, Daniel Shin, Jung Hee Yun, Michele Piccardi, Kim-Fung Chan, Yogesh Luthra, Dheeraj Srinivasan, Srinivasarao Deshmukh, Kalyan Kavalipurapu, Dan Nguyen, Girolamo Gallo, Sumant Ramprasad, Michelle Luo, Qiang Tang, Michele Incarnati, Agostino Macerola, Luigi Pilolli, Luca De Santis, Massimo Rossini, Violante Moschiano, Giovanni Santin, Bernardino Tronca, Hyunseok Lee, Vipul Patel, Ted Pekny, Aaron Yip, Naveen Prabhu, Purval Sule, Trupti Bemalkhedkar, Kiranmayee Upadhyayula, Camila Jaramillo

Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

Design challenge in 3D NAND technology: A 4.8X area- and 1.3X power-efficient 20V charge pump using tier capacitors.

Toru Tanzawa, T. Murakoshi, T. Kamijo, Tomoharu Tanaka, J. J. McNeil, K. Duesman

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2010

A temperature compensation word-line voltage generator for multi-level cell NAND Flash memories.

Toru Tanzawa, Tomoharu Tanaka, Satoru Tamada, Jiro Kishimoto, Sjigekazu Yamada, Koichi Kawai, Takaaki Ichikawa, P. Chiang, Frank Roohparvar

Proceedings of the 36th European Solid-State Circuits Conference, 2010

2009

A 172mm² 32Gb MLC NAND flash memory in 34nm CMOS.

Raymond Zeng, Navneet Chalagalla, Dan Chu, Daniel Elmhurst, Matt Goldman, Chris Haid, Atif Huq, Takaaki Ichikawa, Joel Jorgensen, Owen Jungroth, Nishnat Kajla, Ravinder Kajley, Koichi Kawai, Jiro Kishimoto, Ali Madraswala, Tetsuji Manabe, Vikram Mehta, Midori Morooka, Katie Nguyen, Yoko Oikawa, Bharat Pathak, Rod Rozman, Tom Ryan, Andy Sendrowski, William Sheung, Martin Szwarc, Yasuhiro Takashima, Satoru Tamada, Toru Tanzawa, Tomoharu Tanaka, Mase Taub, Darshak Udeshi, Sjigekazu Yamada, Hiroyuki Yokoyama

Proceedings of the IEEE International Solid-State Circuits Conference, 2009

2002

Circuit techniques for a 1.8-V-only NAND flash memory.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Hiroshi Nakamura

IEEE J. Solid State Circuits, 2002

2001

A dual-page programming scheme for high-speed multigigabit-scale NAND flash memories.

Ken Takeuchi, Tomoharu Tanaka

IEEE J. Solid State Circuits, 2001

1999

A negative V_th cell architecture for highly scalable, excellently noise-immune, and highly reliable NAND flash memories.

Ken Takeuchi, Shinji Satoh, Tomoharu Tanaka, Ken-ichi Imamiya, Koji Sakui

IEEE J. Solid State Circuits, 1999

1998

A multipage cell architecture for high-speed programming multilevel NAND flash memories.

Ken Takeuchi, Tomoharu Tanaka, Toru Tanzawa

IEEE J. Solid State Circuits, 1998

1997

A compact on-chip ECC for low cost flash memories.

Toru Tanzawa, Tomoharu Tanaka, Ken Takeuchi, Riichiro Shirota, Seiichi Aritome, Hiroshi Watanabe, Gertjan Hemink, Kazuhiro Shimizu, Shinji Sato, Yuji Takeuchi, Kazunori Ohuchi

IEEE J. Solid State Circuits, 1997

A dynamic analysis of the Dickson charge pump circuit.

Toru Tanzawa, Tomoharu Tanaka

IEEE J. Solid State Circuits, 1997

A stable programming pulse generator for single power supply flash memories.

Toru Tanzawa, Tomoharu Tanaka

IEEE J. Solid State Circuits, 1997

1996

A double-level-V_th select gate array architecture for multilevel NAND flash memories.

Ken Takeuchi, Tomoharu Tanaka, Hiroshi Nakamura

IEEE J. Solid State Circuits, 1996

1994

A quick intelligent page-programming architecture and a shielded bitline sensing method for 3 V-only NAND flash memory.

Tomoharu Tanaka, Yoshiyuki Tanaka, Hiroshi Nakamura, Koji Sakui, Hideko Oodaira, Riichiro Shirota, Kazunori Ohuchi, Fujio Masuoka, Hisashi Hara

IEEE J. Solid State Circuits, November, 1994

1989

An experimental 4-Mbit CMOS EEPROM with a NAND-structured cell.

Masaki Momodomi, Yasuo Itoh, Riichiro Shirota, Yoshihisa Iwata, Ryozo Nakayama, Ryouhei Kirisawa, Tomoharu Tanaka, Seiichi Aritome, Tetsuo Endoh, Kazunori Ohuchi, Fujjo Masuoka

IEEE J. Solid State Circuits, October, 1989