Tomofumi Yuki

Orcid: 0000-0002-5737-6178

According to our database1, Tomofumi Yuki authored at least 27 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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On csauthors.net:

Bibliography

2023
Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2023

Maximal Simplification of Polyhedral Reductions.
CoRR, 2023

2021
(When) Do Multiple Passes Save Energy?
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021

Parallelizing Compiler Translation Validation Using Happens-Before and Task-Set.
Proceedings of the Ninth International Symposium on Computing and Networking, 2021

2020
Safe Overclocking for CNN Accelerators Through Algorithm-Level Error Detection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Toward Speculative Loop Pipelining for High-Level Synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Towards Generic and Scalable Word-Length Optimization.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

2019
Sparse computation data dependence simplification for efficient compiler-generated inspectors.
Proceedings of the 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, 2019

2018
Sparse Matrix Code Dependence Analysis Simplification at Compile Time.
CoRR, 2018

PCOT: Cache Oblivious Tiling of Polyhedral Programs.
CoRR, 2018

Extending Index-Array Properties for Data Dependence Analysis.
Proceedings of the Languages and Compilers for Parallel Computing, 2018

Enabling Overclocking Through Algorithm-Level Error Detection.
Proceedings of the International Conference on Field-Programmable Technology, 2018

2017
One size does not fit all: Implementation trade-offs for iterative stencil computations on FPGAs.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
EURECA compilation: Automatic optimisation of cycle-reconfigurable circuits.
Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Extended lattice-based memory allocation.
Proceedings of the 25th International Conference on Compiler Construction, 2016

2015
Revisiting loop transformations with x10 clocks.
Proceedings of the ACM SIGPLAN Workshop on X10, Portland, OR, USA, June 15 - 17, 2015, 2015

2014
Toward scalable source level accuracy analysis for floating-point to fixed-point conversion.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

2013
Checking Race Freedom of Clocked X10 Programs.
CoRR, 2013

GeCoS: A framework for prototyping custom hardware design flows.
Proceedings of the 13th IEEE International Working Conference on Source Code Analysis and Manipulation, 2013

Array dataflow analysis for polyhedral X10 programs.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2013

Folklore Confirmed: Compiling for Speed = Compiling for Energy.
Proceedings of the Languages and Compilers for Parallel Computing, 2013

Derivation of efficient FSM from loop nests.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Coarse-Grain Optimization and Code Generation for Embedded Multicore Systems.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
AlphaZ: A System for Design Space Exploration in the Polyhedral Model.
Proceedings of the Languages and Compilers for Parallel Computing, 2012

2011
Model-Driven Engineering and Optimizing Compilers: A Bridge Too Far?
Proceedings of the Model Driven Engineering Languages and Systems, 2011

ompVerify: Polyhedral Analysis for the OpenMP Programmer.
Proceedings of the OpenMP in the Petascale Era - 7th International Workshop on OpenMP, 2011

2010
Automatic creation of tile size selection models.
Proceedings of the CGO 2010, 2010


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