Tomasz Borejko
According to our database1,
Tomasz Borejko
authored at least 21 papers
between 2002 and 2020.
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
Erratum: Borejko, T., et al. NaviSoC: High-Accuracy Low-Power GNSS SoC with an Integrated Application Processor. Sensors 2020, 20, 1069.
Sensors, 2020
Sensors, 2020
2019
DC/DC Buck Converter with Build-in Tuned Sawtooth Wave Generator Using CMOS Technology.
Proceedings of the 26th International Conference on Mixed Design of Integrated Circuits and Systems, 2019
2017
Proceedings of the 24th International Conference Mixed Design of Integrated Circuits and Systems, 2017
2016
Proceedings of the 2016 MIXDES, 2016
Proceedings of the 2016 IEEE East-West Design & Test Symposium, 2016
Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016
2015
A CMOS system-on-chip for physiological parameters acquisition, processing and monitoring.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015
IF polyphase filter design and calibration with back-gate biasing in 28 nm FD-SOI technology.
Proceedings of the 22nd International Conference Mixed Design of Integrated Circuits & Systems, 2015
2012
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
A resistorless current reference source for 65 nm CMOS technology with low sensitivity to process, supply voltage and temperature variations.
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
A comparison of low voltage LNA architectures designed for multistandard GNSS in two 90 nm CMOS technologies.
Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010
2009
Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2009
2008
IEEE Trans. Ind. Electron., 2008
A Resistorless Voltage Reference Source for 90 nm CMOS Technology with Low Sensitivity to Process and Temperature Variations.
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), 2008
2006
DefSim: CMOS Defects on Chip for Research and Education.
Proceedings of the 7th Latin American Test Workshop, 2006
2002
Proceedings of the 17th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2002), 2002