Tom J. Mannos

According to our database, Tom J. Mannos authored at least 7 papers between 2018 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

Self-Assertion-Based Countermeasures Within a RISC-V Microprocessor for Coverage of Information Leakage Faults.

Idris Somoye, Tom J. Mannos, Brian Dziki, Jim Plusquellic

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., June, 2024

An Engineered Minimal-Set Stimulus for Periodic Information Leakage Fault Detection on a RISC-V Microprocessor.

Idris Somoye, Jim Plusquellic, Tom J. Mannos, Brian Dziki

Cryptogr., June, 2024

2022

Information Leakage Analysis Using a Co-Design-Based Fault Injection Technique on a RISC-V Microprocessor.

Jim Plusquellic, Donald E. Owen, Tom J. Mannos, Brian Dziki

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Node Monitoring as a Fault Detection Countermeasure against Information Leakage within a RISC-V Microprocessor.

Donald E. Owen, Jithin Joseph, Jim Plusquellic, Tom J. Mannos, Brian Dziki

Cryptogr., 2022

2019

ASIC STA Path Verification Using Semi-Supervised Learning.

James Obert, Tom J. Mannos

Int. J. Semantic Comput., 2019

Fault Testing a Synthesizable Embedded Processor at Gate Level using UltraScale FPGA Emulation.

Tom J. Mannos, Brian Dziki, Moslema Sharif

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

2018

Semi-Supervised Learning and ASIC Path Verification.

James Obert, Tom J. Mannos

Proceedings of the First International Conference on Artificial Intelligence for Industries, 2018