Tom Glint

Orcid: 0000-0002-4053-0247

According to our database1, Tom Glint authored at least 11 papers between 2020 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2024
COMPRIZE: Assessing the Fusion of Quantization and Compression on DNN Hardware Accelerators.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

DeepFrack: A Comprehensive Framework for Layer Fusion, Face Tiling, and Efficient Mapping in DNN Hardware Accelerators.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Hardware-Software Co-Design of a Collaborative DNN Accelerator for 3D Stacked Memories with Multi-Channel Data.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

CANSim: When to Utilize Synchronous and Asynchronous Routers in Large and Complex NoCs.
Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023
Analysis of Conventional, Near-Memory, and In-Memory DNN Accelerators.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Impact of Optimal Design Point on Performance Metrics of DNN accelerators in FPGA.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2023

Analysis of Quantization Across DNN Accelerator Architecture Paradigms.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNet.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Hardware-Software Codesign of DNN Accelerators Using Approximate Posit Multipliers.
Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

2022
A Fresh Perspective on DNN Accelerators by Performing Holistic Analysis Across Paradigms.
CoRR, 2022

2020
ANSim: A Fast and Versatile Asynchronous Network-On-Chip Simulator.
Proceedings of the 38th IEEE International Conference on Computer Design, 2020


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