Tom English

According to our database, Tom English authored at least 8 papers between 2008 and 2012.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2012

A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT).

John W. Lockwood, Adwait Gupte, Nishit Mehta, Michaela Blott, Tom English, Kees A. Vissers

Proceedings of the IEEE 20th Annual Symposium on High-Performance Interconnects, 2012

2011

Network-on-Chip interconnect for pairing-based cryptographic IP cores.

Tom English, Emanuel M. Popovici, Maurice Keller, William P. Marnane

J. Syst. Archit., 2011

Timing-Driven Power Optimisation and Power-Driven Timing Optimisation of Combinational Circuits.

Rashmi Mehrotra, Tom English, Michel P. Schellekens, Steve Hollands, Emanuel M. Popovici

J. Low Power Electron., 2011

Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators.

Tom English, Emanuel M. Popovici

Proceedings of the NOCS 2011, 2011

2010

Delay dependent power optimisation of combinational circuits using AND-Inverter graphs.

Rashmi Mehrotra, Tom English, Emanuel M. Popovici, Michel P. Schellekens

Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

2009

A low-power pairing-based cryptographic accelerator for embedded security applications.

Tom English, Maurice Keller, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens, William P. Marnane

Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

BSAA: A Switching Activity Analysis and Visualisation Tool for SoC Power Optimisation.

Tom English, Ka Lok Man, Emanuel M. Popovici

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2009

2008

HotSpot: Visualizing dynamic power consumption in RTL designs.

Tom English, Ka Lok Man, Emanuel M. Popovici, Michel P. Schellekens

Proceedings of the 2008 East-West Design & Test Symposium, 2008