Tokuo Kure
According to our database1,
Tokuo Kure
authored at least 5 papers
between 1993 and 1999.
Collaborative distances:
Collaborative distances:
Timeline
1993
1994
1995
1996
1997
1998
1999
0
1
2
3
1
1
1
2
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
1999
1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996
1994
IEEE J. Solid State Circuits, June, 1994
1993
IEEE J. Solid State Circuits, November, 1993
IEEE J. Solid State Circuits, November, 1993