Tokuo Kure

According to our database1, Tokuo Kure authored at least 5 papers between 1993 and 1999.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

1993
1994
1995
1996
1997
1998
1999
0
1
2
3
1
1
1
2

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

1999
Single-electron memory for giga-to-tera bit storage.
Proc. IEEE, 1999

1996
A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.
IEEE J. Solid State Circuits, 1996

1994
A charge recycle refresh for Gb-scale DRAM's in file applications.
IEEE J. Solid State Circuits, June, 1994

1993
256-Mb DRAM circuit technologies for file applications.
IEEE J. Solid State Circuits, November, 1993

Subthreshold current reduction for decoded-driver by self-reverse biasing (DRAMs).
IEEE J. Solid State Circuits, November, 1993


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