Tokuo Kure

According to our database, Tokuo Kure authored at least 3 papers between 1994 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

Single-electron memory for giga-to-tera bit storage.

Kazuo Yano, Tomoyuki Ishii, Toshiaki Sano, Toshiyuki Mine, Fumio Murai, Takashi Hashimoto, Takashi Kobayashi, Tokuo Kure, Koichi Seki

Proc. IEEE, 1999

1996

A 1-V, 100-MHz, 10-mW cache using a separated bit-line memory hierarchy architecture and domino tag comparators.

Hiroyuki Mizuno, Nozomu Matsuzaki, Kenichi Osada, Toshinobu Shinbo, Nagatoshi Ohki, Hiroshi Ishida, Koichiro Ishibashi, Tokuo Kure

IEEE J. Solid State Circuits, 1996

1994

A charge recycle refresh for Gb-scale DRAM's in file applications.

Takayulu Kawahara, Yoshiki Kawajiri, Masashi Horiguchi, Takesada Akiba, Goro Kitsukawa, Tokuo Kure, Masakazu Aoki

IEEE J. Solid State Circuits, June, 1994