Tohru Yamazaki

According to our database, Tohru Yamazaki authored at least 7 papers between 1990 and 1999.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

1999

A 5-GHz-band multifunctional BiCMOS transceiver chip for GMSK modulation wireless systems.

Mohammad Madihian, Tomislav Drenski, Laurent Desclos, Hiroshi Yoshida, Hiroshi Hirabayashi, Tohru Yamazaki

IEEE J. Solid State Circuits, 1999

A 2.125-Gb/s BiCMOS fiber channel transmitter for serial data communications.

Muneo Fukaishi, Satoshi Nakamura, Akio Tajima, Yasushi Kinoshita, Yoshihiko Suemura, Hisamitsu Suzuki, Toshiro Itani, Hidenobu Miyamoto, Naoya Henmi, Tohru Yamazaki, Michio Yotsuyanagi

IEEE J. Solid State Circuits, 1999

1997

A 2-V, 1-10 GHz BiCMOS transceiver chip for multimode wireless communications networks.

Mohammad Madihian, Emmanuel Bak, Hiroshi Yoshida, Hiroshi Hirabayashi, Kyotaka Imai, Yasushi Kinoshita, Tohru Yamazaki, Laurent Desclos

IEEE J. Solid State Circuits, 1997

1996

A 6-ns, 1.5-V, 4-Mb BiCMOS SRAM.

Hideo Toyoshima, Shigeru Kuhara, Koichi Takeda, Kazuyuki Nakamura, Hiloshi Okamura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

IEEE J. Solid State Circuits, 1996

1994

A 220-MHz pipelined 16-Mb BiCMOS SRAM with PLL proportional self-timing generator.

Kazuyuki Nakamura, Shigeru Kuhara, Tohru Kimura, Masahide Takada, Hisamitsu Suzuki, Hiroshi Yoshida, Tohru Yamazaki

IEEE J. Solid State Circuits, November, 1994

1992

A 6-ns ECL 100 K I/O and 8-ns 3.3-V TTL I/O 4-Mb BiCMOS SRAM.

Kazuyuki Nakamura, Takashi Oguri, Takao Atsumo, Masahide Takada, Atsushi Ikemoto, Hisamitsu Suzuki, Tadashi Nishigori, Tohru Yamazaki

IEEE J. Solid State Circuits, November, 1992

1990

A 5-ns 1-Mb ECL BiCMOS SRAM.

Masahide Takada, Kazuyuki Nakamura, Toshio Takeshima, Koichiro Furuta, Tohru Yamazaki, Kiyotaka Imai, Susumu Ohi, Yumi Sekine, Yukio Minato, Hisamitsu Kimuto

IEEE J. Solid State Circuits, October, 1990